This page displays all 「FI」 in main group H10B41/00. |
HB:Handbook | ||||
CC:Concordance |
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Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates [2023.01] | HB | CC | 5F083 | |
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.characterised by the top-view layout [2023.01] | HB | CC | 5F083 | |
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.characterised by three-dimensional arrangements, e.g. with cells on different height levels [2023.01] | HB | CC | 5F083 | |
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..with source and drain on different levels, e.g. with sloping channels [2023.01] | HB | CC | 5F083 | |
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...the channels comprising vertical portions, e.g. U-shaped channels [2023.01] | HB | CC | 5F083 | |
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.characterised by the memory core region [2023.01] | HB | CC | 5F083 | |
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..with a cell select transistor, e.g. NAND [2023.01] | HB | CC | 5F083 | |
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.characterised by the peripheral circuit region [2023.01] | HB | CC | 5F083 | |
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..of a memory region comprising a cell select transistor, e.g. NAND [2023.01] | HB | CC | 5F083 | |
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..Simultaneous manufacture of periphery and memory cells [2023.01] | HB | CC | 5F083 | |
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...comprising only one type of peripheral transistor [2023.01] | HB | CC | 5F083 | |
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....with a control gate layer also being used as part of the peripheral transistor [2023.01] | HB | CC | 5F083 | |
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....with an inter-gate dielectric layer also being used as part of the peripheral transistor [2023.01] | HB | CC | 5F083 | |
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....with a floating-gate layer also being used as part of the peripheral transistor [2023.01] | HB | CC | 5F083 | |
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....with a tunnel dielectric layer also being used as part of the peripheral transistor [2023.01] | HB | CC | 5F083 | |
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...comprising different types of peripheral transistor [2023.01] | HB | CC | 5F083 | |
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.characterised by the boundary region between the core region and the peripheral circuit region [2023.01] | HB | CC | 5F083 | |
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.the control gate being a doped region, e.g. singlepoly memory cell [2023.01] | HB | CC | 5F083 | |
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.the floating gate being an electrode shared by two or more components [2023.01] | HB | CC | 5F083 | |