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F-Term-List

(Not Translated)
4M119 MRAM OR SPIN MEMORY TECHNIQUES
H01L27/105 ,447
H01L27/105,447 AA AA00
PURPOSE 		AA01 AA02 AA03 AA05 AA06 AA07 AA08 AA09 AA10
. Low power consumption . preventing leakage currents . reducing write currents . Accelerating . High reliability . preventing miswriting . preventing variations . adjusting reversal magnetic fields or asteroid curves . reducing leakage magnetic fields
AA11 AA13 AA15 AA17 AA19 AA20
. High integration or microfabrication . Crosstalk prevention . High signal-to-noise (SN) ratios . expanding operating margins . improving processes of manufacture . Other purposes
BB BB00
TYPE OF STORAGE ELEMENT 		BB01 BB03 BB05 BB07
. TMR elements . Giant magneto-resistors . CMR elements . Hall elements
BB11 BB12 BB13 BB14 BB15 BB20
. Transistor types or three-terminal elements . . Field effect transistor (FET) types . . . Spin field effect transistors (FETs) . . . Spin-dependent single electron transistors . . Bipolar types . Other storage elements
CC CC00
MAGNETISATION CONTROL TECHNIQUE 		CC01 CC02 CC03 CC04 CC05 CC06 CC07 CC08 CC09 CC10
. controlling magnetisation by magnetic fields . . controlling magnetisation by current wires for generating magnetic fields . . . by circuits or timing . . . . Combinations of cell structures with timing e.g. toggles . Spin injection magnetisation reversal methods . controlling magnetisation by heat or thermally assisted methods . controlling magnetisation by light or electromagnetic waves . controlling magnetisation by stresses . controlling magnetisation by electric fields . Other magnetisation control techniques
DD DD00
CELL CONFIGURATION 		DD01 DD02 DD03 DD04 DD05 DD06 DD07 DD08 DD09 DD10
. characterised by storage elements . . characterised by layer structures or junctions of storage elements . . . characterised by structures of barrier layers . . . . Constricted current paths or insulating layer nanoholes . . . characterised by structures of free layers . . . characterised by structures of fixed layers . . . characterised by buffer layers or seed layers . . . characterised by cap layers or protective layers . . . SyAF or multilayer ferrimagnetism . . . Double tunnel junction
DD13 DD15 DD17
. . . Junction surfaces being not parallel to substrate surfaces . . . controlling interface structures e.g. roughness control . . . using perpendicular magnetic films
DD22 DD23 DD24 DD25 DD26 DD27
. . characterised by plane shapes of storage elements . . . Crossed types . . . Circular shapes . . . Elliptical types or oval shapes . . . Rectangular shapes . . . Parallelogram or diamond shapes
DD31 DD32 DD33 DD34 DD35 DD36 DD37 DD39
. Selection elements . . Field effect transistors (FETs) . . . MISFETs . . . . Channels being in directions other than horizontal to substrates . . . . TFTs or FETs on silicon-on-insulators (SOIs) . . Bipolar transistors . . Diodes thyristors or rectifiers . Additional L C or R elements
DD41 DD42 DD43 DD44 DD45 DD46 DD47 DD48 DD49 DD50
. Architectures . . Cross point methods . . . including a plurality of storage elements in one cell . . Tr+ storage element methods . . . Cells or units composed of one Tr+ one storage element . . . Cells or units with one Tr+ a plurality of storage elements . . . Cells or units with a plurality of Tr+ one storage element . . . Cells or units with a plurality of Tr+ a plurality of storage elements . . . . Two Tr- two storage elements or twin cells . . . . NAND types
DD51 DD52 DD54 DD55 DD60
. characterised by positional relationships between storage elements . . stacking a plurality of storage elements in vertical directions . characterised by positional relationships between selection elements and storage elements . . Storage elements directly being on SDs of FETs . Techniques relating to other cell configurations
EE EE00
WIRING CONFIGURATION 		EE01 EE02 EE03 EE04 EE05 EE06 EE07 EE08 EE09 EE10
. characterised by write wirings . . characterised by positions of write wirings . . . Write-only wirings being under storage elements . . . Write-only wirings being on storage elements . . . Write-only wirings being at side of storage elements . . . Easy axes of magnetisation and wirings being displaced diagonally . . . Wirings penetrating storage elements . . characterised by shapes of write wirings . . . Meandering . . . with winding shapes
EE11 EE12 EE13 EE14 EE15 EE16 EE17 EE18 EE19 EE20
. Yoke or cladding structures . . forming yokes on two sides of wirings . . forming yokes on three sides of wirings . . forming yoke on four sides of wirings . . forming fully closed magnetic circuits . . having protruded or recessed configurations . . dividing yoke films . . stacked yoke films . . adjusting film thicknesses of yokes . . having auxiliary yokes
EE21 EE22 EE23 EE24 EE25 EE26 EE27 EE28 EE29 EE30
. Bit lines (BLs) . . Only one BL being present in one cell or unit . . A plurality of BLs being present in one cell or unit . . . having write BLs and read BLs separately . . . branching BLs e.g. bypass lines or backing lines . Word lines (WLs) . . Only one word line (WL) being present in one cell or unit . . A plurality of (WLs) being present in one cell or unit . . . having write word lines (WLs) or read word lines (WLs) separately . . . branching WLs e.g. bypass lines or backing lines
EE31 EE33 EE35 EE40
. Power supply lines (Vcc) . Ground lines (GND) . characterised by sharing wirings . Techniques relating to other wirings
FF FF00
CONTACT 		FF01 FF02 FF03 FF04 FF05 FF06 FF07
. characterised by shapes of contacts or processes of manufacture thereof . . Self-aligned contacts . . . using sidewall shapes . . having contact base layers or barrier layers . . having plugs . . having relay pads . . Contact wirings penetrating wiring layers
FF12 FF13 FF14 FF15 FF16 FF17 FF18 FF19
. characterised by positions of contacts . . between storage elements and upper wirings . . between storage elements and lower wirings . . between lower wirings and selection elements . . between storage elements and selection elements without lower wirings . . between selection elements and wirings . . between wirings and auxiliary circuits . . between a plurality of wirings
GG GG00
LAYOUT 		GG01 GG02 GG03 GG05 GG07 GG08 GG10
. Layouts between memory cells or units . Layouts of memory cell arrays . Layouts of memory blocks or chip levels . Auxiliary circuit layouts . Wiring layouts . Contact layouts . Layouts of other configurations
HH HH00
CIRCUIT TECHNIQUE 		HH01 HH02 HH04 HH05 HH07 HH09
. Write circuits . . Drivers . Read circuits . . Sense amplifiers . Address selection circuits . Difference comparators
HH11 HH13 HH15 HH17 HH19 HH20
. Power supply circuits . Reference circuits . Temperature compensation circuits . Block diagrams . Protective circuits . Other circuit techniques
JJ JJ00
PROCESS OF MANUFACTURE 		JJ01 JJ02 JJ03 JJ04 JJ05 JJ07 JJ09 JJ10
. characterised by film forming . . characterised by oxidation methods . . characterised by sputtering methods . . characterised by chemical vapour deposition (CVD) methods . . characterised by ion beam deposition methods . Evaluating or testing techniques . characterised by heat treatments . Laminates (drawings required)
JJ11 JJ12 JJ13 JJ14 JJ15 JJ16 JJ17 JJ18 JJ20
. characterised by processing methods . . characterised by dry etching . . characterised by sputter etching or ion milling . . characterised by wet etching . . Chemical mechanical polishing (CMP) or flattening techniques (drawings required) . . . Damascene techniques (drawings required) . . Processing using liftoff (drawings required) . . Processing using sidewall shape masks (drawings required) . Other processes of manufacture
KK KK00
INTEGRATION OR MIXED-MOUNTING TECHNIQUE 		KK01 KK02 KK03 KK04 KK05 KK06 KK07 KK09 KK10
. Techniques of mixed-mounting with semiconductor elements . . Relationships between memory cell parts and auxiliary circuit parts . . . Simultaneous formation of memory cell parts and auxiliary circuit parts . . Mixed-mounting memories or system large scale integrated (LSI) circuits . . applying spin elements to logic elements . . merging existing semiconductor memories with spin elements . . SOI substrate . characterised by interlayer films . characterised by simulation
KK11 KK12 KK14 KK15 KK16 KK17 KK18 KK20
. Redundancy provision or failure relief . Dummy cells or dummy wirings . Multi-bits . . Multilevels . Mounting techniques . . Pad electrodes or bonding electrodes . Magnetic shielding . Other accumulating or mixed-mounting techniques
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