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This page displays all 「FI」 in main group G06F30/00. |
HB:Handbook | ||||
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CC:Concordance | |||||
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Computer-aided design [CAD] [2020.01] | HB | CC | 5B146 | |
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.Geometric CAD [2020.01] | HB | CC | 5B146 | |
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..Design of design objects' shapes(G06F30/13~30/18 takes precedence, physical-level design of circuits G06F30/39) | HB | CC | 5B146 | |
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..Design using drawings or models in which design objects are abstracted, e.g., block diagrams(G06F30/13~30/18 takes precedence, design of circuits G06F30/30) | HB | CC | 5B146 | |
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..characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD [2020.01] | HB | CC | 5B146 | |
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..Architectural design, e.g. computer-aided architectural design [CAAD] related to design of buildings, bridges, landscapes, production plants or roads [2020.01] | HB | CC | 5B146 | |
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..Vehicle, aircraft or watercraft design [2020.01] | HB | CC | 5B146 | |
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..Mechanical parametric or variational design [2020.01] | HB | CC | 5B146 | |
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..Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling (circuit design at the physical level G06F 30/39; network planning tools for wireless communication networks H04W 16/18) [2020.01] | HB | CC | 5B146 | |
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.Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F 30/30) [2020.01] | HB | CC | 5B146 | |
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..using Petri net models [2020.01] | HB | CC | 5B146 | |
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..using finite element methods [FEM] or finite difference methods [FDM] [2020.01] | HB | CC | 5B146 | |
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..using particle-based methods [2020.01] | HB | CC | 5B146 | |
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..using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model [2020.01] | HB | CC | 5B146 | |
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..using fluid dynamics, e.g. using Navier-Stokes equations or computational fluid dynamics [CFD] [2020.01] | HB | CC | 5B146 | |
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.Circuit design [2020.01] | HB | CC | 5B146 | |
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..Design entry, e.g. editors specifically adapted for circuit design [2020.01] | HB | CC | 5B146 | |
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..Circuit design at the digital level (reconfigurable circuits G06F 30/34) [2020.01] | HB | CC | 5B146 | |
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...Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation [2020.01] | HB | CC | 5B146 | |
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...Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist [2020.01] | HB | CC | 5B146 | |
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...Design verification, e.g. functional simulation or model checking [2020.01] | HB | CC | 5B146 | |
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....using simulation [2020.01] | HB | CC | 5B146 | |
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.....with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation [2020.01] | HB | CC | 5B146 | |
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.....Timing analysis [2020.01] | HB | CC | 5B146 | |
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....using static timing analysis [STA] [2020.01] | HB | CC | 5B146 | |
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....using formal methods, e.g. equivalence checking or property checking [2020.01] | HB | CC | 5B146 | |
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...Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] [2020.01] | HB | CC | 5B146 | |
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...Design optimisation [2020.01] | HB | CC | 5B146 | |
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..for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] [2020.01] | HB | CC | 5B146 | |
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...Logical level [2020.01] | HB | CC | 5B146 | |
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...Physical level, e.g. placement or routing [2020.01] | HB | CC | 5B146 | |
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..Delay-insensitive circuit design, e.g. asynchronous or self-timed [2020.01] | HB | CC | 5B146 | |
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..Circuit design at the analogue level [2020.01] | HB | CC | 5B146 | |
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...Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods [2020.01] | HB | CC | 5B146 | |
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...Design optimisation [2020.01] | HB | CC | 5B146 | |
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..Circuit design at the mixed level of analogue and digital signals [2020.01] | HB | CC | 5B146 | |
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..Circuit design at the physical level (physical level design for reconfigurable circuits G06F 30/347) [2020.01] | HB | CC | 5B146 | |
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...Floor-planning or layout, e.g. partitioning or placement [2020.01] | HB | CC | 5B146 | |
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...Routing (G06F 30/396 takes precedence) [2020.01] | HB | CC | 5B146 | |
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....global [2020.01] | HB | CC | 5B146 | |
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....detailed [2020.01] | HB | CC | 5B146 | |
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...Clock trees [2020.01] | HB | CC | 5B146 | |
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...Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F 1/36) [2020.01] | HB | CC | 5B146 | |