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FI (list display)

  • G06F13/00
    		•  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F 3/00; multi-processor systems G06F 15/16) [4] HB CC 5B114
  • G06F13/10
    		•  .Programme control for peripheral devices (G06F 13/14-G06F 13/42 take precedence) [4] HB CC 5B114
  • G06F13/10,310
    		•  ..Input/output control HB CC 5B114
  • G06F13/10,310@A
    		•  Input/output operation and configuration per se HB CC 5B114
  • G06F13/10,310@B
    		•  CPU to input/output control HB CC 5B114
  • G06F13/10,310@C
    		•  .Start control HB CC 5B114
  • G06F13/10,310@D
    		•  Input/output to CPU control HB CC 5B114
  • G06F13/10,310@E
    		•  Mode control HB CC 5B114
  • G06F13/10,310@Z
    		•  Others HB CC 5B114
  • G06F13/10,320
    		•  ...Input/output control programmes HB CC 5B114
  • G06F13/10,320@A
    		•  Programme selection or patch by input/output HB CC 5B114
  • G06F13/10,320@Z
    		•  Others HB CC 5B114
  • G06F13/10,330
    		•  ....Operating systems HB CC 5B114
  • G06F13/10,330@A
    		•  Data or event management HB CC 5B114
  • G06F13/10,330@B
    		•  Job, task, or programme management HB CC 5B114
  • G06F13/10,330@C
    		•  Input/output management or virtual machines HB CC 5B114
  • G06F13/10,330@D
    		•  Buffer management in the main memory HB CC 5B114
  • G06F13/10,330@Z
    		•  Others HB CC 5B114
  • G06F13/10,340
    		•  ..Input/output device control HB CC 5B114
  • G06F13/10,340@A
    		•  Disk drive control HB CC 5B114
  • G06F13/10,340@B
    		•  .Data transfer on a disk drive HB CC 5B114
  • G06F13/10,340@Z
    		•  Others HB CC 5B114
  • G06F13/12
    		•  ..using hardware independent of the central processor, e.g. channel or peripheral processor [4] HB CC 5B114
  • G06F13/12,310
    		•  ...Channel controller HB CC 5B114
  • G06F13/12,310@A
    		•  Control for upper level devices HB CC 5B114
  • G06F13/12,310@B
    		•  Control in the controller HB CC 5B114
  • G06F13/12,310@C
    		•  Control for lower level devices HB CC 5B114
  • G06F13/12,310@D
    		•  .Activation/termination control HB CC 5B114
  • G06F13/12,310@E
    		•  Channel connection device HB CC 5B114
  • G06F13/12,310@F
    		•  Channel interrupt control HB CC 5B114
  • G06F13/12,310@G
    		•  Sub-channel HB CC 5B114
  • G06F13/12,310@H
    		•  .Sub-channel start control HB CC 5B114
  • G06F13/12,310@J
    		•  Multiplexer channel HB CC 5B114
  • G06F13/12,310@P
    		•  Control by a micro-programme HB CC 5B114
  • G06F13/12,310@Q
    		•  .Cooperation between the micro-programme and hardware HB CC 5B114
  • G06F13/12,310@R
    		•  .Micro-programme selection HB CC 5B114
  • G06F13/12,310@Z
    		•  Others HB CC 5B114
  • G06F13/12,320
    		•  ....Channel commands HB CC 5B114
  • G06F13/12,320@A
    		•  CCW per se HB CC 5B114
  • G06F13/12,320@B
    		•  CCW storing HB CC 5B114
  • G06F13/12,320@C
    		•  CCW retrieval HB CC 5B114
  • G06F13/12,320@D
    		•  CCW buffer HB CC 5B114
  • G06F13/12,320@E
    		•  CCW execution/termination process HB CC 5B114
  • G06F13/12,320@F
    		•  Command chaining HB CC 5B114
  • G06F13/12,320@G
    		•  .Termination process in command chaining HB CC 5B114
  • G06F13/12,320@H
    		•  Data chaining HB CC 5B114
  • G06F13/12,320@Z
    		•  Others HB CC 5B114
  • G06F13/12,330
    		•  ....Data transfer HB CC 5B114
  • G06F13/12,330@A
    		•  Data transfer control HB CC 5B114
  • G06F13/12,330@B
    		•  .Address control HB CC 5B114
  • G06F13/12,330@C
    		•  .Transferred volume control HB CC 5B114
  • G06F13/12,330@D
    		•  .Block transfer HB CC 5B114
  • G06F13/12,330@E
    		•  .Control according to the data pattern HB CC 5B114
  • G06F13/12,330@F
    		•  Channel buffer HB CC 5B114
  • G06F13/12,330@G
    		•  .Channel buffer area management HB CC 5B114
  • G06F13/12,330@H
    		•  .Byte/word conversion or byte mark HB CC 5B114
  • G06F13/12,330@P
    		•  In virtual storage HB CC 5B114
  • G06F13/12,330@Q
    		•  .Multiplexed virtual storage HB CC 5B114
  • G06F13/12,330@R
    		•  Address expansion HB CC 5B114
  • G06F13/12,330@S
    		•  Address mode specification HB CC 5B114
  • G06F13/12,330@T
    		•  Cache memory HB CC 5B114
  • G06F13/12,330@Z
    		•  Others HB CC 5B114
  • G06F13/12,340
    		•  ...Input/output controllers HB CC 5B114
  • G06F13/12,340@A
    		•  Input/output controllers per se HB CC 5B114
  • G06F13/12,340@B
    		•  .Data/command buffer HB CC 5B114
  • G06F13/12,340@C
    		•  .CPU role participation (data conversion, etc.) HB CC 5B114
  • G06F13/12,340@D
    		•  Upper interface HB CC 5B114
  • G06F13/12,340@E
    		•  Lower interface HB CC 5B114
  • G06F13/12,340@F
    		•  .Multi-input/output scanning or identification HB CC 5B114
  • G06F13/12,340@G
    		•  .Format conversion for data, etc. HB CC 5B114
  • G06F13/12,340@H
    		•  .Input/output control mode decision HB CC 5B114
  • G06F13/12,340@J
    		•  .Input/output control programmes HB CC 5B114
  • G06F13/12,340@Z
    		•  Others HB CC 5B114
  • G06F13/12,350
    		•  ...Input/output adapters HB CC 5B114
  • G06F13/14
    		•  .Handling requests for interconnection or transfer [4] HB CC 5B114
  • G06F13/14,310
    		•  ..Input/output selection control HB CC 5B114
  • G06F13/14,310@A
    		•  Input/output exclusive control HB CC 5B114
  • G06F13/14,310@B
    		•  .CPU-to-input/output exclusive control table HB CC 5B114
  • G06F13/14,310@C
    		•  .Exclusive CPU codes provided for input/output HB CC 5B114
  • G06F13/14,310@D
    		•  .Control by a switching circuit HB CC 5B114
  • G06F13/14,310@E
    		•  Failure or deadlock countermeasures HB CC 5B114
  • G06F13/14,310@F
    		•  Switching control HB CC 5B114
  • G06F13/14,310@G
    		•  Input/output processors HB CC 5B114
  • G06F13/14,310@H
    		•  Access path control HB CC 5B114
  • G06F13/14,310@J
    		•  Interrupt processing HB CC 5B114
  • G06F13/14,310@K
    		•  Selection by detecting a change HB CC 5B114
  • G06F13/14,310@Y
    		•  Others using multiple CPUs HB CC 5B114
  • G06F13/14,310@Z
    		•  Others HB CC 5B114
  • G06F13/14,320
    		•  ..Address control HB CC 5B114
  • G06F13/14,320@A
    		•  Address setting HB CC 5B114
  • G06F13/14,320@B
    		•  Address selection (including input/output selection in general) HB CC 5B114
  • G06F13/14,320@C
    		•  Having multiple addresses HB CC 5B114
  • G06F13/14,320@D
    		•  Common addresses HB CC 5B114
  • G06F13/14,320@E
    		•  Address sending technology HB CC 5B114
  • G06F13/14,320@F
    		•  Address setting by implementation HB CC 5B114
  • G06F13/14,320@G
    		•  Simultaneous sending of the address and data (including serial) HB CC 5B114
  • G06F13/14,320@H
    		•  Logical - physical addresses HB CC 5B114
  • G06F13/14,320@J
    		•  Memory mapped input/output HB CC 5B114
  • G06F13/14,320@K
    		•  Address expansion (address specification register, etc.) HB CC 5B114
  • G06F13/14,320@Z
    		•  Others HB CC 5B114
  • G06F13/14,330
    		•  ..Configuration control HB CC 5B114
  • G06F13/14,330@A
    		•  Configuration control information in general HB CC 5B114
  • G06F13/14,330@B
    		•  .Information collection HB CC 5B114
  • G06F13/14,330@C
    		•  .Input/output accommodation control HB CC 5B114
  • G06F13/14,330@D
    		•  .Input/output existence recognition control HB CC 5B114
  • G06F13/14,330@E
    		•  .Re-configuration HB CC 5B114
  • G06F13/14,330@F
    		•  SVP panel console HB CC 5B114
  • G06F13/14,330@G
    		•  .Data passing HB CC 5B114
  • G06F13/14,330@Z
    		•  Others HB CC 5B114
  • G06F13/16
    		•  ..for access to memory bus (G06F 13/28 takes precedence) [4] HB CC 5B160
  • G06F13/16,510
    		•  ...Memory bus organization or structure HB CC 5B160
  • G06F13/16,510@A
    		•  Dedicated bus HB CC 5B160
  • G06F13/16,510@B
    		•  Ring bus HB CC 5B160
  • G06F13/16,510@C
    		•  Bus connection/disconnection HB CC 5B160
  • G06F13/16,510@D
    		•  .Multi-bus selection or switching HB CC 5B160
  • G06F13/16,510@E
    		•  Input/output circuit control HB CC 5B160
  • G06F13/16,510@F
    		•  .External memory access control HB CC 5B160
  • G06F13/16,510@G
    		•  Address transmission HB CC 5B160
  • G06F13/16,510@H
    		•  .Address split transmission HB CC 5B160
  • G06F13/16,510@J
    		•  .Data transmission using an address bus HB CC 5B160
  • G06F13/16,510@Z
    		•  Others HB CC 5B160
  • G06F13/16,520
    		•  ...Memory bus access control HB CC 5B160
  • G06F13/16,520@A
    		•  Bus mode access cyclic control HB CC 5B160
  • G06F13/16,520@B
    		•  Transmission/reception control HB CC 5B160
  • G06F13/16,520@C
    		•  Buffer control HB CC 5B160
  • G06F13/16,520@Z
    		•  Others HB CC 5B160
  • G06F13/18
    		•  ...with priority control [4] HB CC 5B160
  • G06F13/18,510
    		•  ....Access control (12/00, 57 and 013/36 take precedence.) HB CC 5B160
  • G06F13/18,510@A
    		•  Control between the CPU and input/output HB CC 5B160
  • G06F13/18,510@B
    		•  Bus occupancy/exclusive control HB CC 5B160
  • G06F13/18,510@Z
    		•  Others HB CC 5B160
  • G06F13/20
    		•  ..for access to input/output bus [4] HB CC 5B061
  • G06F13/22
    		•  ...using successive scanning, e.g. polling (G06F 13/24 takes precedence) [4] HB CC 5B061
  • G06F13/24
    		•  ...using interrupt (G06F 13/32 takes precedence) [4] HB CC 5B061
  • G06F13/24,310
    		•  ....Interrupt to the central processing unit HB CC 5B061
  • G06F13/24,310@A
    		•  Interrupt signal generation/formation HB CC 5B061
  • G06F13/24,310@B
    		•  Use of a daisy chain HB CC 5B061
  • G06F13/24,310@C
    		•  Interrupt vector HB CC 5B061
  • G06F13/24,310@D
    		•  Interrupt register or mask register HB CC 5B061
  • G06F13/24,310@E
    		•  Interrupt information or status HB CC 5B061
  • G06F13/24,310@F
    		•  Interrupt level HB CC 5B061
  • G06F13/24,310@G
    		•  Interrupt source (cause) scan HB CC 5B061
  • G06F13/24,310@H
    		•  Interrupt to multiple CPUs HB CC 5B061
  • G06F13/24,310@Z
    		•  Others HB CC 5B061
  • G06F13/24,320
    		•  .....Interrupt request HB CC 5B061
  • G06F13/24,330
    		•  .....Interrupt acceptance HB CC 5B061
  • G06F13/24,340
    		•  ....Interrupt to channel control HB CC 5B061
  • G06F13/26
    		•  ....with priority control [4] HB CC 5B061
  • G06F13/28
    		•  ...using burst mode transfer, e.g. direct memory access, cycle steal (G06F 13/32 takes precedence) [4] HB CC 5B061
  • G06F13/28,310
    		•  ....Direct memory access HB CC 5B061
  • G06F13/28,310@A
    		•  Control in general HB CC 5B061
  • G06F13/28,310@B
    		•  Request selection HB CC 5B061
  • G06F13/28,310@C
    		•  Commands HB CC 5B061
  • G06F13/28,310@E
    		•  Data transfer control in general HB CC 5B061
  • G06F13/28,310@F
    		•  Data transfer width control HB CC 5B061
  • G06F13/28,310@G
    		•  Data transfer volume control HB CC 5B061
  • G06F13/28,310@H
    		•  Continuous data transfer (data chain) HB CC 5B061
  • G06F13/28,310@J
    		•  With a buffer HB CC 5B061
  • G06F13/28,310@K
    		•  With search/operation HB CC 5B061
  • G06F13/28,310@L
    		•  In-(inter-)memory transfer (including refresh) HB CC 5B061
  • G06F13/28,310@M
    		•  Transfer address control HB CC 5B061
  • G06F13/28,310@N
    		•  Bank address or address expansion HB CC 5B061
  • G06F13/28,310@P
    		•  DMA bus (split bus) HB CC 5B061
  • G06F13/28,310@Q
    		•  CPU halt control HB CC 5B061
  • G06F13/28,310@Y
    		•  Image data DMA HB CC 5B061
  • G06F13/28,310@Z
    		•  Others HB CC 5B061
  • G06F13/28,320
    		•  ....Cycle steal HB CC 5B061
  • G06F13/28,330
    		•  ....CPU related processes HB CC 5B061
  • G06F13/30
    		•  ....with priority control [4] HB CC 5B061
  • G06F13/32
    		•  ...using combination of interrupt and burst mode transfer [4] HB CC 5B061
  • G06F13/34
    		•  ....with priority control [4] HB CC 5B061
  • G06F13/36
    		•  ..for access to common bus or bus system [4] HB CC 5B061
  • G06F13/36,310
    		•  ...Bus adapter HB CC 5B061
  • G06F13/36,310@A
    		•  Passive type adapter: Circuit HB CC 5B061
  • G06F13/36,310@B
    		•  Passive type adapter: Address-based control HB CC 5B061
  • G06F13/36,310@C
    		•  Passive type adapter: Adapter between active buses HB CC 5B061
  • G06F13/36,310@D
    		•  Passive type adapter: Others HB CC 5B061
  • G06F13/36,310@E
    		•  Active type adapter: In general HB CC 5B061
  • G06F13/36,310@F
    		•  Active type adapter: In-adapter buffer management HB CC 5B061
  • G06F13/36,310@Z
    		•  Others HB CC 5B061
  • G06F13/36,320
    		•  ....Bus type conversion HB CC 5B061
  • G06F13/36,320@A
    		•  Adapter between different buses (different protocols) HB CC 5B061
  • G06F13/36,320@B
    		•  Data width conversion HB CC 5B061
  • G06F13/36,320@Z
    		•  Others HB CC 5B061
  • G06F13/36,510
    		•  ...Bus protocol HB CC 5B061
  • G06F13/36,520
    		•  ...Bus access HB CC 5B061
  • G06F13/36,520@A
    		•  Advance control HB CC 5B061
  • G06F13/36,520@B
    		•  Control depending on the status of the remote device HB CC 5B061
  • G06F13/36,520@D
    		•  Bus changeover switch HB CC 5B061
  • G06F13/36,520@E
    		•  Address data multiplexed time dividing transmission HB CC 5B061
  • G06F13/36,520@Z
    		•  Others HB CC 5B061
  • G06F13/36,530
    		•  ...Special buses HB CC 5B061
  • G06F13/36,530@A
    		•  Matrix organization HB CC 5B061
  • G06F13/36,530@B
    		•  Multi-bus (partial use of buses) HB CC 5B061
  • G06F13/36,530@C
    		•  Loop buses HB CC 5B061
  • G06F13/36,530@Z
    		•  Others HB CC 5B061
  • G06F13/362
    		•  ...with centralised access control [5] HB CC 5B061
  • G06F13/362,510
    		•  ....Priority selection processes HB CC 5B061
  • G06F13/362,510@A
    		•  Priority selection circuits HB CC 5B061
  • G06F13/362,510@B
    		•  Use of multiple circuits (parallel, multi-stage) HB CC 5B061
  • G06F13/362,510@C
    		•  Control with busy/ready HB CC 5B061
  • G06F13/362,510@D
    		•  Control in general HB CC 5B061
  • G06F13/362,510@E
    		•  Priority change: Control in general HB CC 5B061
  • G06F13/362,510@F
    		•  Priority change: Priority registers (RAM, ROM) HB CC 5B061
  • G06F13/362,510@G
    		•  Priority change: Change for each access HB CC 5B061
  • G06F13/362,510@H
    		•  Priority change: Depending on the occupancy times or non-acceptance times HB CC 5B061
  • G06F13/362,510@J
    		•  Priority change: Emergency process request HB CC 5B061
  • G06F13/362,510@Z
    		•  Others HB CC 5B061
  • G06F13/362,520
    		•  ....Bus request selection HB CC 5B061
  • G06F13/362,520@A
    		•  Depending on the variable order HB CC 5B061
  • G06F13/362,520@B
    		•  Bus occupancy continuation, resume, or termination HB CC 5B061
  • G06F13/362,520@Z
    		•  Others HB CC 5B061
  • G06F13/364
    		•  ....using independent requests or grants, e.g. using separated request and grant lines [5] HB CC 5B061
  • G06F13/366
    		•  ....using a centralised polling arbiter [5] HB CC 5B061
  • G06F13/366,510
    		•  .....Request scanning HB CC 5B061
  • G06F13/366,510@A
    		•  Scanning with a counter HB CC 5B061
  • G06F13/366,510@B
    		•  Scan pulse propagation HB CC 5B061
  • G06F13/366,510@C
    		•  Scan control in general HB CC 5B061
  • G06F13/366,510@Z
    		•  Others HB CC 5B061
  • G06F13/368
    		•  ...with decentralised access control [5] HB CC 5B061
  • G06F13/368@A
    		•  Token bus system HB CC 5B061
  • G06F13/368@Z
    		•  Others HB CC 5B061
  • G06F13/37
    		•  ....using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing [5] HB CC 5B061
  • G06F13/37@A
    		•  Multiple chains HB CC 5B061
  • G06F13/37@B
    		•  Grouping HB CC 5B061
  • G06F13/37@C
    		•  Bypass HB CC 5B061
  • G06F13/37@D
    		•  Return chain HB CC 5B061
  • G06F13/37@E
    		•  Reciprocal chain HB CC 5B061
  • G06F13/37@F
    		•  Special chain HB CC 5B061
  • G06F13/37@G
    		•  Request acknowledgement control HB CC 5B061
  • G06F13/37@Z
    		•  Others HB CC 5B061
  • G06F13/372
    		•  ....using a time-dependent priority, e.g. individually loaded time counters or time slot [5] HB CC 5B061
  • G06F13/372@A
    		•  Control with delay time HB CC 5B061
  • G06F13/372@B
    		•  Occupied period control (interrupt, resume, continuation) HB CC 5B061
  • G06F13/372@C
    		•  Time slot control HB CC 5B061
  • G06F13/372@Z
    		•  Others HB CC 5B061
  • G06F13/374
    		•  ....using a self-select method with individual priority code comparator [5] HB CC 5B061
  • G06F13/376
    		•  ....using a contention resolving method, e.g. collision detection, collision avoidance [5] HB CC 5B061
  • G06F13/378
    		•  ....using a parallel poll method [5] HB CC 5B061
  • G06F13/38
    		•  .Information transfer, e.g. on bus (G06F 13/14 takes precedence) [4] HB CC 5B077
  • G06F13/38,310
    		•  ..Data buffer technology HB CC 5B077
  • G06F13/38,310@A
    		•  Buffer control in general HB CC 5B077
  • G06F13/38,310@B
    		•  Data transfer control HB CC 5B077
  • G06F13/38,310@C
    		•  Buffer area management HB CC 5B077
  • G06F13/38,310@D
    		•  In-buffer data (volume) management HB CC 5B077
  • G06F13/38,310@E
    		•  Alternate buffer HB CC 5B077
  • G06F13/38,310@F
    		•  RAM buffer HB CC 5B077
  • G06F13/38,310@G
    		•  Multi-stage buffer HB CC 5B077
  • G06F13/38,310@H
    		•  Multi-area bi-directional buffer HB CC 5B077
  • G06F13/38,310@Z
    		•  Others HB CC 5B077
  • G06F13/38,320
    		•  ..Interface technology HB CC 5B077
  • G06F13/38,320@A
    		•  Mode selection/switching HB CC 5B077
  • G06F13/38,320@Z
    		•  Others HB CC 5B077
  • G06F13/38,330
    		•  ...Data transfer HB CC 5B077
  • G06F13/38,330@A
    		•  Batch transfer HB CC 5B077
  • G06F13/38,330@B
    		•  Inter-input/output direct transfer HB CC 5B077
  • G06F13/38,330@C
    		•  Address/control bus utilisation HB CC 5B077
  • G06F13/38,330@Z
    		•  Others HB CC 5B077
  • G06F13/38,340
    		•  ....Inter-processor data transfer HB CC 5B077
  • G06F13/38,340@A
    		•  Use of a bus HB CC 5B077
  • G06F13/38,340@B
    		•  Via a main memory HB CC 5B077
  • G06F13/38,340@C
    		•  Via a buffer HB CC 5B077
  • G06F13/38,340@D
    		•  Control signal passing HB CC 5B077
  • G06F13/38,340@E
    		•  Via a channel adapter HB CC 5B077
  • G06F13/38,340@F
    		•  .Channel adapter programme HB CC 5B077
  • G06F13/38,340@G
    		•  Special adapters HB CC 5B077
  • G06F13/38,340@Z
    		•  Others HB CC 5B077
  • G06F13/38,350
    		•  ....Serial transfer HB CC 5B077
  • G06F13/40
    		•  ..Bus structure [4] HB CC 5B077
  • G06F13/40,310
    		•  ...Bus configuration technology HB CC 5B077
  • G06F13/42
    		•  ..Bus transfer protocol, e.g. handshake; Synchronisation [4] HB CC 5B077
  • G06F13/42,310
    		•  ...Transfer protocol HB CC 5B077
  • G06F13/42,320
    		•  ....Response acknowledgement HB CC 5B077
  • G06F13/42,320@A
    		•  Response acknowledgement in general HB CC 5B077
  • G06F13/42,320@B
    		•  Dummy response HB CC 5B077
  • G06F13/42,320@C
    		•  Data stream type HB CC 5B077
  • G06F13/42,320@D
    		•  Use of the tag's both ends (two tags) HB CC 5B077
  • G06F13/42,320@Z
    		•  Others HB CC 5B077
  • G06F13/42,330
    		•  ....Bi-directional bus control HB CC 5B077
  • G06F13/42,340
    		•  ....Synchronous bus control HB CC 5B077
  • G06F13/42,340@A
    		•  Synchronous bus in general HB CC 5B077
  • G06F13/42,340@B
    		•  Co-use of the synchronous and asynchronous buses HB CC 5B077
  • G06F13/42,340@Z
    		•  Others HB CC 5B077
  • G06F13/42,350
    		•  ....Timing control HB CC 5B077
  • G06F13/42,350@A
    		•  Signal synchronization HB CC 5B077
  • G06F13/42,350@B
    		•  Clock switching or passing HB CC 5B077
  • G06F13/42,350@C
    		•  Timing selection by input/output HB CC 5B077
  • G06F13/42,350@Z
    		•  Others HB CC 5B077
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