Japanese
close

F-Term-List

5B160 MEMORY SYSTEM
G06F12/00 ,550-12/06,570@Z;13/16-13/18,510@Z
G06F12/00,550-12/06,570@Z;13/16-13/18,510@Z AA AA00
ALLOCATION, RELOCATION 		AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10
(Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) . . Address conversion . Free area management . . Garbage collection
AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20
(Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) . Divisional allocation . Overlay structure/control . Load control, Resident/non-resident control . Roll-in/Roll-out . Memory storage control of information (data)
AB AB00
ADDRESS CONTROL 		AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10
. Addressing mode switching control (Not Translated) (Not Translated) (Not Translated) . Multiple address register control (Not Translated) (Not Translated) . Address control for specific devices . . for DMA (Not Translated)
AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20
. Address divisional control (Not Translated) . . Row (RAS)/Column (CAS) addresses . . . Block specification part/in-block address . . Upper address control (carry-over) . . Boundary variable control, variable-length address technology . Serial address control . . using counters . . Page-mode access control . . generating serial addresses in a specific range (repeatedly)
AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30
. Indirect address control (Not Translated) (Not Translated) . . accessing external devices (memory), or the like . Address modification/address conversion control . . Logical to Physical address conversion . . calculating effective address . . Address update control . . . by update instruction . All-clear, identical data write control
AC AC00
OBJECTS OF AA, AB 		AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10
(Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated)
AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20
(Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated) . Work area, buffer area (Not Translated) (Not Translated)
BA BA00
ADDRESS EXTENSION 		BA01 BA02 BA03 BA04 BA05 BA06 BA07 BA08 BA09 BA10
. Extension mode control, switching control . . Normal mode/Extension mode . . . Expanded memory access area (window) . . . by execution instruction type . . . by access type, use . . CPU access/peripheral device access . . . with dedicated address extension mechanism . . Conversion table (map) control (Not Translated) (Not Translated)
BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19
. Address extension control (Not Translated) (Not Translated) . . Address extension by adding register values (Not Translated) (Not Translated) . . Address bit extension, bit addition . . . Upper/lower bit split transmission . . . using data buses
BB BB00
MEMORY SPACE EXPANSION 		BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10
. Bank switching factors . . Bank switching instruction (program) execution (Not Translated) (Not Translated) . . Accessing specific address . . Instruction fetch/data fetch . . Execution instruction type . . Program type (Not Translated) . . Execution time, timer
BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20
. Bank register value (bank) setting means . . I/O instruction execution . . Accessing specific address . Configurations of bank registers (Not Translated) (Not Translated) . having dedicated bank area (Not Translated) (Not Translated) . relating to switching control programs (areas)
CA CA00
ACCESS CONTROL 		CA01 CA02 CA03 CA04 CA05 CA06 CA07 CA08 CA09 CA10
. Access mode control (e.g., privilege mode control) (Not Translated) . High-speed access . . High-speed serial access . . . Pipeline control, overlap control . . . Preceding control of access (Not Translated) . Time-division control of access (Not Translated) . Handling contention between access request and refresh request
CA11 CA12 CA13 CA14 CA15 CA16 CA17 CA18 CA19 CA20
. Block (bank) access control . . Multi-block simultaneous access . . . accessing the same address (location) . . . loading/storing data in parallel . . varying timing by block . . relating to load/store type . Data transfer, data movement . . Data transfer in the same memory . . changing address set for data . . Measures against overlap of transfer source and transfer destination
CB CB00
LOAD/STORE CONTROL 		CB01 CB02 CB03 CB04 CB05 CB06 CB07 CB08 CB09 CB10
. Load buffer/store buffer control . Load-store with data modification . . Load/store with logical operation . . correcting the contents in memory by load/store . Handling load-store contention (Not Translated) (Not Translated) . Load and store to the same address . . loading from store buffer . . Temporary saving, holding of overwritten part
CC CC00
ACCESS TIMING CONTROL 		CC01 CC02 CC03 CC04 CC05 CC06 CC07 CC08 CC09 CC10
. Timing signal control . . Cycle length control, wait cycle control . . Clock control (clock control/clock switching) . Access synchronous/asynchronous control (Not Translated) (Not Translated) . Multi-type access cycle control . . Instruction cycle and data cycle . . Load cycle and store cycle . . changing cycle for serial access
CD CD00
ACCESS REQUEST CONTROL 		CD01 CD02 CD03 CD04 CD05 CD06 CD07 CD08
. Request buffer (queue) management (Not Translated) (Not Translated) . . . Reordering, priority control . . . Request synthesis, request combining . . . Request invalidation, request cancel (Not Translated) . . . Request transmission timing control
CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20
. Access contention control . . Access priority control (Not Translated) (Not Translated) . . Busy control, busy determination . . . Priority control to non-busy device (bank) . . Occupancy control, exclusive control (Not Translated) (Not Translated) . . avoiding (preventing, releasing) deadlock
DA DA00
VARIABLE-LENGTH WORDS, PARTIAL ACCESS CONTROL 		DA01 DA02 DA03 DA04 DA05 DA06 DA07 DA08 DA09 DA10
. Address boundary processing . . Byte/word access switching control . . processing by single access . Partial write, partial read (Not Translated) (Not Translated) . . converting partial-write to full-write . Data compression, data extension . Record format change . Data bit length expansion, bit addition
GA GA00
IMAGE MEMORY SYSTEMS 		GA01 GA02 GA03 GA04 GA05 GA06 GA07 GA08 GA09 GA10
. Image memory configurations . . Bit-mapped memory configurations . . . Plane-type memory configurations . . . Pixel-type memory configurations . . dividing an image data area into cells . . setting special address to memory blocks . Address types for image memory . . Two-dimensional (X, Y) address . . . using page mode access function . . converted to one-dimensional address
GA11 GA12 GA13 GA14 GA15 GA16 GA17 GA18 GA19 GA20
. Rectangular area (M*N) access technology . Adjacent area (center-specified) access technology . Image data processing in word unit . . Bit access control in word . . . Bit boundary control . Address control for image data processing . . Rotation, vertical/horizontal conversion processing . . Compression, expansion processing . Measures against contention between display and data processing . . using two-port memory
HA HA00
INTERLEAVING CONTROL 		HA01 HA02 HA03 HA04 HA05 HA06 HA08 HA10
. Configuration control, configuration change . . switching interleaving (the number of ways) . . sharing or reducing control circuits or registers . . Measures against faulty banks . Address setting for interleaving . . Even bank configuration . controlling data element (arrangement) intervals . restoring interleaved data
KA KA00
SHARED MEMORY SYSTEMS 		KA01 KA02 KA03 KA04 KA05 KA06 KA07 KA08 KA09 KA10
. including multiple processing systems . including multiple CPUs . including CPU and peripheral devices . having one shared memory . . including multiple banks (Not Translated) (Not Translated) (Not Translated) (Not Translated) (Not Translated)
MB MB00
MEMORY BUS TECHNOLOGY 		MB01 MB02 MB03 MB04 MB05 MB06 MB07 MB08 MB09 MB10
. controlling switching/connecting multiple buses . . Multiple buses of the same type . . Buses different in property/bus width/type . Controlling connection between multiple systems (buses) . . using two-port memory . Bus mode control (Not Translated) . with different data width and bus width . Technology of reducing bus lines . having memory-dedicated bus in addition to common bus
MM MM00
MEMORY MODULE CONFIGURATION, MANAGEMENT TECHNOLOGY 		MM01 MM02 MM03 MM04 MM05 MM06 MM07 MM08 MM09 MM10
. Memory module configuration/control . . including ROM and RAM . . including modules of different access speeds . . including modules of different capacities . . controlling R/W mode of RAM . controlling mounting of memory modules (Not Translated) (Not Translated) . Detachable, memory card, cartridge (Not Translated)
MM11 MM12 MM13 MM14 MM15 MM16 MM17 MM18 MM19 MM20
. setting address to memory modules . . setting to address decoder, or the like . . changing set address . . . due to failure of memory module . selecting memory module, detecting access . . using addresses . . using module specification information . Memory modules with additional functions . . Address generation/update function . . Logical operation function
NA NA00
TECHNOLOGY OF IMPROVING RELIABILITY 		NA01 NA02 NA03
. improving reliability . . extending lifetime, managing lifetime . . . Wear leveling
TOP