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  • G06F12/00
    		•  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F 3/06) [4, 5, 2006.01] HB CC 5B160
  • G06F12/00,550
    		•  .Memory systems or memory architectures HB CC 5B160
  • G06F12/00,550@A
    		•  Initialisation or clear control (G06F 12/02 or G06F 12/06 take precedence) HB CC 5B160
  • G06F12/00,550@B
    		•  Refresh control HB CC 5B160
  • G06F12/00,550@C
    		•  Configuration change control (G06F 12/06 or G06F 12/16 take precedence) HB CC 5B160
  • G06F12/00,550@E
    		•  Power saving control (by selecting block G06F 12/06, 515 takes precedence) HB CC 5B160
  • G06F12/00,550@K
    		•  Characterized by physical structure of memory system HB CC 5B160
  • G06F12/00,550@Z
    		•  Others HB CC 5B160
  • G06F12/00,560
    		•  .Load/store control HB CC 5B160
  • G06F12/00,560@A
    		•  Load/store control HB CC 5B160
  • G06F12/00,560@B
    		•  .Load/store buffer control or load/store concurrent process HB CC 5B160
  • G06F12/00,560@C
    		•  .Pipeline control, e.g. read and write alternate execution, data collision avoidance or write after read processing HB CC 5B160
  • G06F12/00,560@D
    		•  .Load and store contention HB CC 5B160
  • G06F12/00,560@E
    		•  .Matching between load and store addresses HB CC 5B160
  • G06F12/00,560@F
    		•  .Logical operation function HB CC 5B160
  • G06F12/00,560@G
    		•  .Search or compare function (address comparison G06F 12/00, 560 E) HB CC 5B160
  • G06F12/00,560@Z
    		•  Others HB CC 5B160
  • G06F12/00,564
    		•  ..Timing control (G06F 12/06 takes precedence) HB CC 5B160
  • G06F12/00,564@A
    		•  Timing control HB CC 5B160
  • G06F12/00,564@B
    		•  .Memory start control HB CC 5B160
  • G06F12/00,564@C
    		•  .Timing changeover control HB CC 5B160
  • G06F12/00,564@D
    		•  .Propagation delay countermeasure HB CC 5B160
  • G06F12/00,564@Z
    		•  Others HB CC 5B160
  • G06F12/00,570
    		•  .Shared memory systems (G06F 12/02, G06F 12/04 or G06F 12/06 take precedence) HB CC 5B160
  • G06F12/00,570@A
    		•  Access authority control HB CC 5B160
  • G06F12/00,570@B
    		•  .Time dividing control HB CC 5B160
  • G06F12/00,570@C
    		•  .Two-port memories HB CC 5B160
  • G06F12/00,570@Z
    		•  Others HB CC 5B160
  • G06F12/00,571
    		•  ..Access request control HB CC 5B160
  • G06F12/00,571@A
    		•  Access request control HB CC 5B160
  • G06F12/00,571@B
    		•  .Priority order control HB CC 5B160
  • G06F12/00,571@C
    		•  .Between storage and controller HB CC 5B160
  • G06F12/00,571@Z
    		•  Others HB CC 5B160
  • G06F12/00,572
    		•  ..Exclusive control HB CC 5B160
  • G06F12/00,572@A
    		•  Exclusive control HB CC 5B160
  • G06F12/00,572@B
    		•  .Deadlock countermeasures HB CC 5B160
  • G06F12/00,572@Z
    		•  Others HB CC 5B160
  • G06F12/00,580
    		•  .Image data processing data systems (G06F 12/02, G06F 12/04 or G06F 12/06 take precedence) HB CC 5B160
  • G06F12/00,590
    		•  .List data processing memory systems HB CC 5B160
  • G06F12/00,591
    		•  ..Garbage collection HB CC 5B160
  • G06F12/00,592
    		•  .Vector data processing memory systems (G06F 12/06 takes precedence) HB CC 5B160
  • G06F12/00,593
    		•  .Data flow control memory systems HB CC 5B160
  • G06F12/00,594
    		•  .Stack control memory systems HB CC 5B160
  • G06F12/00,595
    		•  .Register control memory systems HB CC 5B160
  • G06F12/00,597
    		•  .Memory system of specific memory type HB CC 5B160
  • G06F12/00,597@C
    		•  For clock synchronized type memory (G06F 12/00, 597 N or G06F 12/00, 597 R take precedence) HB CC 5B160
  • G06F12/00,597@D
    		•  For double data rate type memory HB CC 5B160
  • G06F12/00,597@N
    		•  For memory that has cash region in chip HB CC 5B160
  • G06F12/00,597@R
    		•  For protocol type memory HB CC 5B160
  • G06F12/00,597@U
    		•  For non-volatile memory capable of programming to be erasable HB CC 5B160
  • G06F12/00,597@Z
    		•  Others HB CC 5B160
  • G06F12/00,599
    		•  .Other memory systems HB CC 5B160
  • G06F12/02
    		•  .Addressing or allocation; Relocation (programme address sequencing G06F 9/00; arrangements for selecting an address in a digital store G11C 8/00) [4] HB CC 5B160
  • G06F12/02,510
    		•  ..Storage area management HB CC 5B160
  • G06F12/02,510@A
    		•  Storage area management HB CC 5B160
  • G06F12/02,510@B
    		•  .First end, i.e. minimum address and last end, i.e. maximum address allocation HB CC 5B160
  • G06F12/02,510@M
    		•  Shared memory use area control HB CC 5B160
  • G06F12/02,510@Z
    		•  Others HB CC 5B160
  • G06F12/02,520
    		•  ..Area acquisition or release control HB CC 5B160
  • G06F12/02,520@A
    		•  Load control HB CC 5B160
  • G06F12/02,520@B
    		•  Overlay control HB CC 5B160
  • G06F12/02,520@Z
    		•  Others HB CC 5B160
  • G06F12/02,530
    		•  ...Free area management HB CC 5B160
  • G06F12/02,530@A
    		•  Free area space computation or indication HB CC 5B160
  • G06F12/02,530@B
    		•  Bitmap management HB CC 5B160
  • G06F12/02,530@C
    		•  Area compression, i.e. compaction HB CC 5B160
  • G06F12/02,530@D
    		•  Overflow countermeasures or reserved area management HB CC 5B160
  • G06F12/02,530@E
    		•  Free area creation HB CC 5B160
  • G06F12/02,530@Z
    		•  Others HB CC 5B160
  • G06F12/02,540
    		•  ...Buffer area management HB CC 5B160
  • G06F12/02,550
    		•  ..Address control HB CC 5B160
  • G06F12/02,550@A
    		•  Address register organisation or structure HB CC 5B160
  • G06F12/02,550@B
    		•  Multiple addressing means changeover HB CC 5B160
  • G06F12/02,550@C
    		•  Multiplexed data read or write address control HB CC 5B160
  • G06F12/02,550@D
    		•  Delay circuit address control HB CC 5B160
  • G06F12/02,550@E
    		•  Lookup table address control HB CC 5B160
  • G06F12/02,550@Z
    		•  Others HB CC 5B160
  • G06F12/02,560
    		•  ...Instruction addressing or operand addressing HB CC 5B160
  • G06F12/02,560@A
    		•  Addressing or address qualification HB CC 5B160
  • G06F12/02,560@B
    		•  .Continuous address control (G06F 12/00, 580 takes precedence) HB CC 5B160
  • G06F12/02,560@C
    		•  .Instruction advance control or instruction prefetching HB CC 5B160
  • G06F12/02,560@D
    		•  .Indirect address control HB CC 5B160
  • G06F12/02,560@Z
    		•  Others HB CC 5B160
  • G06F12/02,570
    		•  ...Address conversion or address expansion HB CC 5B160
  • G06F12/02,570@A
    		•  Address conversion control HB CC 5B160
  • G06F12/02,570@D
    		•  .Boundary address or common area control HB CC 5B160
  • G06F12/02,570@E
    		•  .Conversion or expansion mode and normal mode switching HB CC 5B160
  • G06F12/02,570@F
    		•  .Conversion time reduction or conversion omission HB CC 5B160
  • G06F12/02,570@G
    		•  .Space size or page size change HB CC 5B160
  • G06F12/02,570@H
    		•  .Virtual data transfer or transfer time reduction HB CC 5B160
  • G06F12/02,570@J
    		•  .Rectangular area, i.e. two-dimensional area conversion HB CC 5B160
  • G06F12/02,570@K
    		•  Shared memory address conversion HB CC 5B160
  • G06F12/02,570@L
    		•  .Prefix conversion HB CC 5B160
  • G06F12/02,570@M
    		•  input/output equipment, e.g. address conversion for DMA or channel HB CC 5B160
  • G06F12/02,570@Q
    		•  Expansion address bit addition HB CC 5B160
  • G06F12/02,570@Z
    		•  Others HB CC 5B160
  • G06F12/02,580
    		•  ...Continuous address control HB CC 5B160
  • G06F12/02,580@A
    		•  Data transfer control or transfer instruction control HB CC 5B160
  • G06F12/02,580@B
    		•  .In-memory data transfer processing HB CC 5B160
  • G06F12/02,580@C
    		•  .Address overlapping countermeasures HB CC 5B160
  • G06F12/02,580@D
    		•  .Cyclic address control HB CC 5B160
  • G06F12/02,580@E
    		•  Rectangular area, i.e. two-dimensional area address control HB CC 5B160
  • G06F12/02,580@F
    		•  .Address direction or interval control HB CC 5B160
  • G06F12/02,580@G
    		•  X-direction address or Y-direction address control HB CC 5B160
  • G06F12/02,580@H
    		•  Data array address control HB CC 5B160
  • G06F12/02,580@J
    		•  Continuous address access that uses burst mode HB CC 5B160
  • G06F12/02,580@Z
    		•  Others HB CC 5B160
  • G06F12/02,590
    		•  ...DRAM access control, e.g. CAS or RAS control HB CC 5B160
  • G06F12/02,590@A
    		•  CAS control or RAS control HB CC 5B160
  • G06F12/02,590@B
    		•  .Address continuous detection page mode control HB CC 5B160
  • G06F12/02,590@C
    		•  .Page incrementing control HB CC 5B160
  • G06F12/02,590@Z
    		•  Others HB CC 5B160
  • G06F12/04
    		•  ..Addressing variable-length words or parts of words [4] HB CC 5B160
  • G06F12/04,510
    		•  ...Variable-length word access control HB CC 5B160
  • G06F12/04,510@A
    		•  Variable-length word data string addressing HB CC 5B160
  • G06F12/04,510@B
    		•  Addressing control in word units or byte units HB CC 5B160
  • G06F12/04,510@C
    		•  .Address continuous detection buffer access HB CC 5B160
  • G06F12/04,510@D
    		•  .Co-existence of data with different lengths or back (-shifted) data addressing HB CC 5B160
  • G06F12/04,510@E
    		•  Involves serial/parallel conversion control or parallel/serial conversion control HB CC 5B160
  • G06F12/04,510@F
    		•  .Two-port memories with serial port and parallel port HB CC 5B160
  • G06F12/04,510@G
    		•  Conversion between MSB system and LSB system, i.e. involving Endian conversion HB CC 5B160
  • G06F12/04,510@Z
    		•  Others HB CC 5B160
  • G06F12/04,520
    		•  ...Partial access control HB CC 5B160
  • G06F12/04,520@A
    		•  Byte access control HB CC 5B160
  • G06F12/04,520@B
    		•  Bit access control HB CC 5B160
  • G06F12/04,520@C
    		•  .Multi-word particular bit position access HB CC 5B160
  • G06F12/04,520@D
    		•  Partial access request control HB CC 5B160
  • G06F12/04,520@Z
    		•  Others HB CC 5B160
  • G06F12/04,530
    		•  ...Data compression or extraction HB CC 5B160
  • G06F12/04,540
    		•  ...Address boundary control HB CC 5B160
  • G06F12/04,540@A
    		•  Byte alignment control HB CC 5B160
  • G06F12/04,540@B
    		•  Bit alignment control HB CC 5B160
  • G06F12/04,540@C
    		•  Access data width changeover control HB CC 5B160
  • G06F12/04,540@Z
    		•  Others HB CC 5B160
  • G06F12/06
    		•  ..Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication (G06F 12/08 takes precedence) [4] HB CC 5B160
  • G06F12/06,510
    		•  ...Implemented block identification or detection HB CC 5B160
  • G06F12/06,510@A
    		•  Identification or detection HB CC 5B160
  • G06F12/06,510@B
    		•  .Identification information reading HB CC 5B160
  • G06F12/06,510@C
    		•  .Written data reading HB CC 5B160
  • G06F12/06,510@D
    		•  Non-implementation countermeasures or address overflow countermeasures HB CC 5B160
  • G06F12/06,510@Z
    		•  Others HB CC 5B160
  • G06F12/06,515
    		•  ...Address setting or block selection HB CC 5B160
  • G06F12/06,515@A
    		•  Selection with address decoders HB CC 5B160
  • G06F12/06,515@B
    		•  .Variable settings HB CC 5B160
  • G06F12/06,515@C
    		•  .Different spaces or space expansion countermeasures HB CC 5B160
  • G06F12/06,515@D
    		•  Address comparison with a memory board HB CC 5B160
  • G06F12/06,515@E
    		•  .Combination of start address and capacity HB CC 5B160
  • G06F12/06,515@F
    		•  ..Conveyance to the next board HB CC 5B160
  • G06F12/06,515@G
    		•  .Upper device, e.g. setting by CPU HB CC 5B160
  • G06F12/06,515@H
    		•  Selection control HB CC 5B160
  • G06F12/06,515@J
    		•  .Selection control between high speed memory and low speeed memory HB CC 5B160
  • G06F12/06,515@K
    		•  .Selection control between ROM and RAM HB CC 5B160
  • G06F12/06,515@L
    		•  .Selection control between inner memory and external memory HB CC 5B160
  • G06F12/06,515@M
    		•  .Selection control between input/output space HB CC 5B160
  • G06F12/06,515@N
    		•  .Multi-block simultaneous selection, e.g. identical data writing and clear HB CC 5B160
  • G06F12/06,515@P
    		•  Virtual data transfer or transfer time reduction by setting changes HB CC 5B160
  • G06F12/06,515@Q
    		•  Setting change for faulty block countermeasures HB CC 5B160
  • G06F12/06,515@R
    		•  Address overflow countermeasures; non-implementation countermeasures HB CC 5B160
  • G06F12/06,515@Z
    		•  Others HB CC 5B160
  • G06F12/06,520
    		•  ...Memory organisation HB CC 5B160
  • G06F12/06,520@A
    		•  With program memories and data memories HB CC 5B160
  • G06F12/06,520@D
    		•  Memory content change HB CC 5B160
  • G06F12/06,520@E
    		•  .Patch or ROM content correction HB CC 5B160
  • G06F12/06,520@F
    		•  Loading IPL or ROM contents into RAM HB CC 5B160
  • G06F12/06,520@G
    		•  RAM writing limitation HB CC 5B160
  • G06F12/06,520@H
    		•  External output memories HB CC 5B160
  • G06F12/06,520@Z
    		•  Others HB CC 5B160
  • G06F12/06,521
    		•  ....Control data width, e.g. in word unit or in byte unit HB CC 5B160
  • G06F12/06,521@A
    		•  Control in word unit or in byte unit HB CC 5B160
  • G06F12/06,521@B
    		•  Partial access control or specific bock selection access HB CC 5B160
  • G06F12/06,521@C
    		•  .Plain memory access HB CC 5B160
  • G06F12/06,521@D
    		•  .Two-dimensional data multi-direction, i.e. vertical/horizontal simultaneous access HB CC 5B160
  • G06F12/06,521@E
    		•  Byte alignment control HB CC 5B160
  • G06F12/06,521@F
    		•  Bit alignment control HB CC 5B160
  • G06F12/06,521@G
    		•  Different bit lengths control or multi-bit length switching HB CC 5B160
  • G06F12/06,521@H
    		•  .Bit width switching with the bit length by the accessing device HB CC 5B160
  • G06F12/06,521@J
    		•  .Co-existence of memory devices with different bit lengths HB CC 5B160
  • G06F12/06,521@Z
    		•  Others HB CC 5B160
  • G06F12/06,522
    		•  ....Transfer control between high-speed memory and low-speed memory HB CC 5B160
  • G06F12/06,522@A
    		•  Transfer control between high-speed memory and low-speed memory HB CC 5B160
  • G06F12/06,522@B
    		•  .Execution by loading in a high-speed memory HB CC 5B160
  • G06F12/06,522@C
    		•  .Storing part of words into a high-speed memory HB CC 5B160
  • G06F12/06,522@D
    		•  .Storing frequently used data into a high-speed memory HB CC 5B160
  • G06F12/06,522@Z
    		•  Others HB CC 5B160
  • G06F12/06,523
    		•  ....Continuous address control HB CC 5B160
  • G06F12/06,523@A
    		•  Multi-block simultaneous selection HB CC 5B160
  • G06F12/06,523@B
    		•  .Address continuous detection buffer access HB CC 5B160
  • G06F12/06,523@C
    		•  Multi-block order selection HB CC 5B160
  • G06F12/06,523@Z
    		•  Others HB CC 5B160
  • G06F12/06,524
    		•  ....Memory packs or removable memories HB CC 5B160
  • G06F12/06,525
    		•  ....Multi-block simultaneous access HB CC 5B160
  • G06F12/06,525@A
    		•  Multi-block simultaneous access HB CC 5B160
  • G06F12/06,525@B
    		•  .Simultaneous execution of writing and reading HB CC 5B160
  • G06F12/06,525@C
    		•  .Block-to-block direct data transfer HB CC 5B160
  • G06F12/06,525@D
    		•  .Common address data batch transfer HB CC 5B160
  • G06F12/06,525@Z
    		•  Others HB CC 5B160
  • G06F12/06,530
    		•  ...Dedicated memory control or distributed type shared memory systems HB CC 5B160
  • G06F12/06,530@A
    		•  Dedicated or shared control HB CC 5B160
  • G06F12/06,530@B
    		•  .Area control HB CC 5B160
  • G06F12/06,530@C
    		•  .Dedicated memory loading, i.e. copying HB CC 5B160
  • G06F12/06,530@D
    		•  Dedicated memory access HB CC 5B160
  • G06F12/06,530@E
    		•  .Partial common area creation HB CC 5B160
  • G06F12/06,530@F
    		•  .Common or identical data creation HB CC 5B160
  • G06F12/06,530@Z
    		•  Others HB CC 5B160
  • G06F12/06,540
    		•  ...Interleave control HB CC 5B160
  • G06F12/06,540@A
    		•  Configuration control HB CC 5B160
  • G06F12/06,540@B
    		•  .Number of ways control HB CC 5B160
  • G06F12/06,540@C
    		•  .Bank address control HB CC 5B160
  • G06F12/06,540@D
    		•  .Control circuit sharing HB CC 5B160
  • G06F12/06,540@E
    		•  Bank control HB CC 5B160
  • G06F12/06,540@F
    		•  .Bank switching control HB CC 5B160
  • G06F12/06,540@G
    		•  .Element pitch control HB CC 5B160
  • G06F12/06,540@Z
    		•  Others HB CC 5B160
  • G06F12/06,550
    		•  ...Access request control HB CC 5B160
  • G06F12/06,550@A
    		•  Access request control HB CC 5B160
  • G06F12/06,550@B
    		•  .Multi-bank simultaneous access or block transfer HB CC 5B160
  • G06F12/06,550@C
    		•  .Access route switching HB CC 5B160
  • G06F12/06,550@Z
    		•  Others HB CC 5B160
  • G06F12/06,560
    		•  ...Memory space expansion HB CC 5B160
  • G06F12/06,560@A
    		•  Expansion memory address HB CC 5B160
  • G06F12/06,560@B
    		•  .Expansion area, e.g. window, control HB CC 5B160
  • G06F12/06,560@C
    		•  .Loading expansion memory data into normal memory HB CC 5B160
  • G06F12/06,560@Z
    		•  Others HB CC 5B160
  • G06F12/06,570
    		•  ....Bank switching control HB CC 5B160
  • G06F12/06,570@A
    		•  Bank switching control HB CC 5B160
  • G06F12/06,570@B
    		•  .Program-to-program linkage, e.g. call or jump HB CC 5B160
  • G06F12/06,570@C
    		•  .Programme type or programme selection HB CC 5B160
  • G06F12/06,570@D
    		•  ..Interrupt control HB CC 5B160
  • G06F12/06,570@E
    		•  .IPL HB CC 5B160
  • G06F12/06,570@F
    		•  .Execution instruction type HB CC 5B160
  • G06F12/06,570@G
    		•  ..Writing/reading HB CC 5B160
  • G06F12/06,570@H
    		•  .With instruction bank and data bank HB CC 5B160
  • G06F12/06,570@J
    		•  .Specific address detection HB CC 5B160
  • G06F12/06,570@K
    		•  .Switching with hardware, e.g. switch HB CC 5B160
  • G06F12/06,570@L
    		•  .Switching with a timer HB CC 5B160
  • G06F12/06,570@M
    		•  .Bank switching detection in the bank HB CC 5B160
  • G06F12/06,570@N
    		•  .Input/Output devices, e.g. bank registers for DMA or channel HB CC 5B160
  • G06F12/06,570@Z
    		•  Others HB CC 5B160
  • G06F12/08
    		•  ..in hierarchically structured memory systems, e.g. virtual memory systems [4, 2016.01] HB CC 5B205
  • G06F12/0802
    		•  ...Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches [2016.01] HB CC 5B205
  • G06F12/0804
    		•  ....with main memory updating (G06F12/0806 takes precedence) [2016.01] HB CC 5B205
  • G06F12/0804,100
    		•  .....Transfer or write back from cache memory to main memory HB CC 5B205
  • G06F12/0804,105
    		•  .....store buffer HB CC 5B205
  • G06F12/0804,107
    		•  ......store buffer for cache memory HB CC 5B205
  • G06F12/0804,109
    		•  ......store buffer for store through control HB CC 5B205
  • G06F12/0804,111
    		•  ......reading on CPU from store buffer HB CC 5B205
  • G06F12/0806
    		•  ....Multiuser, multiprocessor or multiprocessing cache systems [2016.01] HB CC 5B205
  • G06F12/0806,100
    		•  .....relating to multi CPU (Coincidence Control of cache memory G06f12/0815 takes precedence) HB CC 5B205
  • G06F12/0808
    		•  .....with cache invalidating means (G06F12/0815 takes precedence) [2016.01] HB CC 5B205
  • G06F12/0811
    		•  .....with multilevel cache hierarchies [2016.01] HB CC 5B205
  • G06F12/0813
    		•  .....with a network or matrix configuration [2016.01] HB CC 5B205
  • G06F12/0815
    		•  .....Cache consistency protocols [2016.01] HB CC 5B205
  • G06F12/0817
    		•  ......using directory methods [2016.01] HB CC 5B205
  • G06F12/0831
    		•  ......using a bus scheme, e.g. with bus monitoring or watching means [2016.01] HB CC 5B205
  • G06F12/0831,100
    		•  .......for accessing main memory peripheral, e.g. I/O or DMA HB CC 5B205
  • G06F12/0837
    		•  ......with software control, e.g. non-cacheable data [2016.01] HB CC 5B205
  • G06F12/084
    		•  .....with a shared cache [2016.01] HB CC 5B205
  • G06F12/0842
    		•  .....for multiprocessing or multitasking [2016.01] HB CC 5B205
  • G06F12/0844
    		•  ....Multiple simultaneous or quasi-simultaneous cache accessing [2016.01] HB CC 5B205
  • G06F12/0846
    		•  .....Cache with multiple tag or data arrays being simultaneously accessible [2016.01] HB CC 5B205
  • G06F12/0846,100
    		•  ......Divided cache, e.g. cache with command and operand divided HB CC 5B205
  • G06F12/0846,105
    		•  .......Command cache and data cache HB CC 5B205
  • G06F12/0846,110
    		•  ......Cache with interleave addressing HB CC 5B205
  • G06F12/0853
    		•  .....Cache with multiport tag or data arrays [2016.01] HB CC 5B205
  • G06F12/0855
    		•  .....Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) [2016.01] HB CC 5B205
  • G06F12/0855,100
    		•  ......by multiple requester HB CC 5B205
  • G06F12/0855,110
    		•  ......with reload from main memory HB CC 5B205
  • G06F12/0862
    		•  ....with prefetch [2016.01] HB CC 5B205
  • G06F12/0862,100
    		•  .....start prefetch separate from ordinary fetch HB CC 5B205
  • G06F12/0862,105
    		•  .....prefetch subject to be determined by access history HB CC 5B205
  • G06F12/0862,110
    		•  .....with command set having cache operation command HB CC 5B205
  • G06F12/0864
    		•  ....using pseudo-associative means, e.g. set-associative or hashing [2016.01] HB CC 5B205
  • G06F12/0866
    		•  ....for peripheral storage systems, e.g. disk cache [2016.01] HB CC 5B205
  • G06F12/0866,100
    		•  .....Disc cache memory HB CC 5B205
  • G06F12/0866,105
    		•  .....related to channels HB CC 5B205
  • G06F12/0868
    		•  .....Data transfer between cache memory and other subsystems, e.g. storage devices or host systems [2016.01] HB CC 5B205
  • G06F12/0868,100
    		•  ......Data transfer between disc cache memory and disc device HB CC 5B205
  • G06F12/0868,105
    		•  .......transfer or write back fromdisc cache memory to disc device HB CC 5B205
  • G06F12/0868,110
    		•  .......transfer from disc device to disc cache memory HB CC 5B205
  • G06F12/0871
    		•  .....Allocation or management of cache space [2016.01] HB CC 5B205
  • G06F12/0871,100
    		•  ......controlled by compiler HB CC 5B205
  • G06F12/0873
    		•  .....Mapping of cache memory to specific storage devices or parts thereof [2016.01] HB CC 5B205
  • G06F12/0875
    		•  ....with dedicated cache, e.g. instruction or stack [2016.01] HB CC 5B205
  • G06F12/0875,100
    		•  .....for limited data HB CC 5B205
  • G06F12/0875,102
    		•  ......for vector data HB CC 5B205
  • G06F12/0875,104
    		•  ......for matrix data HB CC 5B205
  • G06F12/0875,106
    		•  ......for image data HB CC 5B205
  • G06F12/0875,108
    		•  ......for stack data HB CC 5B205
  • G06F12/0875,110
    		•  ......for microprogram HB CC 5B205
  • G06F12/0877
    		•  ....Cache access modes [2016.01] HB CC 5B205
  • G06F12/0877,100
    		•  .....read or write of unaligned data HB CC 5B205
  • G06F12/0877,105
    		•  .....partial writing HB CC 5B205
  • G06F12/0877,107
    		•  ......partial writing on cache memory HB CC 5B205
  • G06F12/0877,109
    		•  ......using cache memory for partial writing on main memory HB CC 5B205
  • G06F12/0879
    		•  .....Burst mode [2016.01] HB CC 5B205
  • G06F12/0882
    		•  .....Page mode [2016.01] HB CC 5B205
  • G06F12/0884
    		•  .....Parallel mode, e.g. in parallel with main memory or CPU [2016.01] HB CC 5B205
  • G06F12/0886
    		•  .....Variable-length word access [2016.01] HB CC 5B205
  • G06F12/0888
    		•  ....using selective caching, e.g. bypass [2016.01] HB CC 5B205
  • G06F12/0888,100
    		•  .....Memory bypass HB CC 5B205
  • G06F12/0888,102
    		•  ......relating to storing control for which specific data is not stored up in cache memory HB CC 5B205
  • G06F12/0888,104
    		•  ......relating to data transfer control which bypass cache memory to transfer toward CPU HB CC 5B205
  • G06F12/0891
    		•  ....using clearing, invalidating or resetting means [2016.01] HB CC 5B205
  • G06F12/0893
    		•  ....Caches characterised by their organisation or structure [2016.01] HB CC 5B205
  • G06F12/0893,100
    		•  .....Cache memory within main memory system HB CC 5B205
  • G06F12/0893,105
    		•  .....having characteritic with chip HB CC 5B205
  • G06F12/0893,107
    		•  ......having characteristic with cache memory elements HB CC 5B205
  • G06F12/0893,109
    		•  ......having characteristic with chip terminal HB CC 5B205
  • G06F12/0893,111
    		•  ......having characteristic with arrangment on chip HB CC 5B205
  • G06F12/0895
    		•  .....of parts of caches, e.g. directory or tag array [2016.01] HB CC 5B205
  • G06F12/0895,100
    		•  ......Tag, directory HB CC 5B205
  • G06F12/0895,102
    		•  .......with variable block size HB CC 5B205
  • G06F12/0895,104
    		•  .......mixture of different block sizes HB CC 5B205
  • G06F12/0895,106
    		•  .......with variable mapping HB CC 5B205
  • G06F12/0895,108
    		•  .......index address selection HB CC 5B205
  • G06F12/0895,110
    		•  .......with characeristic in tag information update HB CC 5B205
  • G06F12/0895,112
    		•  .......tag bit for replacement control HB CC 5B205
  • G06F12/0895,114
    		•  .......tag bit for matching control HB CC 5B205
  • G06F12/0895,116
    		•  .......forecasting access position HB CC 5B205
  • G06F12/0895,118
    		•  .......storing only a portion of data in a block HB CC 5B205
  • G06F12/0895,120
    		•  .......copy tag memory HB CC 5B205
  • G06F12/0897
    		•  .....with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) [2016.01] HB CC 5B205
  • G06F12/0897,100
    		•  ......for amongst cache to have inclusion relation HB CC 5B205
  • G06F12/0897,105
    		•  ......for amongst cache, number of data duplication is small HB CC 5B205
  • G06F12/0897,110
    		•  ......Cache memory storage for data expeled by others HB CC 5B205
  • G06F12/0897,115
    		•  ......secondary cache with no direct connection to memory bus HB CC 5B205
  • G06F12/0897,120
    		•  ......having secondary cache being shared HB CC 5B205
  • G06F12/10
    		•  ...Address translation [4, 2016.01] HB CC 5B205
  • G06F12/1009
    		•  ....using page tables, e.g. page table structures [2016.01] HB CC 5B205
  • G06F12/1009,100
    		•  .....Page fault HB CC 5B205
  • G06F12/1009,105
    		•  .....R bit and C bit for page HB CC 5B205
  • G06F12/1018
    		•  .....involving hashing techniques, e.g. inverted page tables [2016.01] HB CC 5B205
  • G06F12/1027
    		•  ....using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] [2016.01] HB CC 5B205
  • G06F12/1027,100
    		•  .....invalidating TLB HB CC 5B205
  • G06F12/1027,105
    		•  .....with multiple TLB HB CC 5B205
  • G06F12/1027,110
    		•  ......TLB for command and TLB for data HB CC 5B205
  • G06F12/1027,115
    		•  ......TLB layer HB CC 5B205
  • G06F12/1027,120
    		•  .....process for TLB miss hit HB CC 5B205
  • G06F12/1036
    		•  .....for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) [2016.01] HB CC 5B205
  • G06F12/1036,100
    		•  ......for virtual machine HB CC 5B205
  • G06F12/1045
    		•  .....associated with a data cache [2016.01] HB CC 5B205
  • G06F12/1072
    		•  ....Decentralised address translation, e.g. in distributed shared memory systems [2016.01] HB CC 5B205
  • G06F12/1081
    		•  ....for peripheral access to main memory, e.g. direct memory access [DMA] [2016.01] HB CC 5B205
  • G06F12/109
    		•  ....for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) [2016.01] HB CC 5B205
  • G06F12/109,100
    		•  .....with characteristic in shared space control HB CC 5B205
  • G06F12/109,105
    		•  .....access register conversion HB CC 5B205
  • G06F12/109,110
    		•  .....for virtual machine HB CC 5B205
  • G06F12/109,115
    		•  ......split allocation of real memory HB CC 5B205
  • G06F12/109,120
    		•  ......split allocation for host virtual space HB CC 5B205
  • G06F12/12
    		•  ...Replacement control [4, 2016.01] HB CC 5B205
  • G06F12/121
    		•  ....using replacement algorithms [2016.01] HB CC 5B205
  • G06F12/121,100
    		•  .....dynamic change of replacment control HB CC 5B205
  • G06F12/122
    		•  .....of the least frequently used [LFU] type, e.g. with individual count value [2016.01] HB CC 5B205
  • G06F12/123
    		•  .....with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list [2016.01] HB CC 5B205
  • G06F12/126
    		•  .....with special data handling, e.g. priority of data or instructions, handling errors or pinning [2016.01] HB CC 5B205
  • G06F12/126,100
    		•  ......based on data priority HB CC 5B205
  • G06F12/126,105
    		•  ......for data resident HB CC 5B205
  • G06F12/127
    		•  ......using additional replacement algorithms [2016.01] HB CC 5B205
  • G06F12/128
    		•  .....adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel [2016.01] HB CC 5B205
  • G06F12/14
    		•  .Protection against unauthorised use of memory [4] HB CC 5B017
  • G06F12/14,510
    		•  ..Space and region HB CC 5B017
  • G06F12/14,510@A
    		•  Space and region, general HB CC 5B017
  • G06F12/14,510@D
    		•  .Address system HB CC 5B017
  • G06F12/14,510@E
    		•  .Virtual storage system [TLB], ring system and key system HB CC 5B017
  • G06F12/14,510@Z
    		•  Others HB CC 5B017
  • G06F12/16
    		•  .Protection against loss of memory contents [4] HB CC 5B018
    TOP