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This page displays all 「FI」 in main group G06F9/00. |
HB:Handbook | ||||
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CC:Concordance | |||||
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Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10) [2018.01] | HB | CC | 5B070 | |
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.using wired connections, e.g. plugboard [2006.01] | HB | CC | 5B070 | |
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.using record carriers containing only program instructions (G06F9/06 takes precedence) [2006.01] | HB | CC | 5B070 | |
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.using stored programs, i.e. using an internal store of processing equipment to receive or retain programs [2006.01] | HB | CC | 5B070 | |
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..Microcontrol or microprogram arrangements [2006.01] | HB | CC | 5B105 | |
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...Configuration of control or memory arrangements | HB | CC | 5B105 | |
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Two-level micro-programming | HB | CC | 5B105 | |
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Using a portion of main memory as the control or memory range | HB | CC | 5B105 | |
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Using a portion of main memory and control memory as the control or memory range | HB | CC | 5B105 | |
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Virtual control memory | HB | CC | 5B105 | |
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Cache for micro-code | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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...Comprehending micro-instructions | HB | CC | 5B105 | |
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Modifying micro-instructions | HB | CC | 5B105 | |
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.Controlling indirect functions by macro-information | HB | CC | 5B105 | |
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.Controlling indirect functions with micro-address information | HB | CC | 5B105 | |
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Multiplexing micro-fields | HB | CC | 5B105 | |
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Micro-instructions with variable length | HB | CC | 5B105 | |
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Generating fixed data | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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...Bus or register configurations | HB | CC | 5B105 | |
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Bus configurations | HB | CC | 5B105 | |
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.serial buses | HB | CC | 5B105 | |
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Register control | HB | CC | 5B105 | |
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Processing control | HB | CC | 5B105 | |
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Initializing | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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...Timing control | HB | CC | 5B105 | |
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Controlling basic clocks | HB | CC | 5B105 | |
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Synchronisation control with external equipment | HB | CC | 5B105 | |
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Timer control | HB | CC | 5B105 | |
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Low or high speed control memories | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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...Specifying top address of micro-programmes | HB | CC | 5B105 | |
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Specifying top address in general | HB | CC | 5B105 | |
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Processing of firmware macro-instructions | HB | CC | 5B105 | |
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Processing undefined or extended macro instructions | HB | CC | 5B105 | |
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Processing particular macro instructions | HB | CC | 5B105 | |
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Combinations of hardware control and micro-control | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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...Interruption processing | HB | CC | 5B105 | |
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...Correcting or changing micro-programmes | HB | CC | 5B105 | |
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...Measures for malfunctions | HB | CC | 5B105 | |
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Checking micro-sequence e.g. measures for runaways | HB | CC | 5B105 | |
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.Measures for faulty accesses to unused ranges | HB | CC | 5B105 | |
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Checking control memories | HB | CC | 5B105 | |
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.Protecting control memories | HB | CC | 5B105 | |
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Checking micro-instructions | HB | CC | 5B105 | |
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Tracing micro-programs | HB | CC | 5B105 | |
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stopping address | HB | CC | 5B105 | |
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Retrying or restarting | HB | CC | 5B105 | |
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Maintenance panel or data display | HB | CC | 5B105 | |
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Micro-diagnosing | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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...Loading of the microprogram [2006.01] | HB | CC | 5B105 | |
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....Loading initial microprogramming | HB | CC | 5B105 | |
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....Dynamic microprogramming | HB | CC | 5B105 | |
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...Address formation of the next microinstruction (G06F9/28 takes precedence) [2006.01] | HB | CC | 5B105 | |
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....subroutine | HB | CC | 5B105 | |
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....Branching | HB | CC | 5B105 | |
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Branching control in general | HB | CC | 5B105 | |
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Jump between pages | HB | CC | 5B105 | |
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Indirect branching | HB | CC | 5B105 | |
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Micro sequencer | HB | CC | 5B105 | |
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Circuits for determining conditions | HB | CC | 5B105 | |
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specific branch instruction, e.g. skip instructions | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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....special micro sequence, e.g. loop control, macro fetch sequence | HB | CC | 5B105 | |
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Controlling loop | HB | CC | 5B105 | |
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Macro fetch sequence | HB | CC | 5B105 | |
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Pathfinder memory | HB | CC | 5B105 | |
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Macro/micro mixed sequence | HB | CC | 5B105 | |
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Multi-micro-programmes | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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...Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel [2006.01] | HB | CC | 5B105 | |
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....Advanced control | HB | CC | 5B105 | |
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Advanced control of micro-programmes | HB | CC | 5B105 | |
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.Increased micro-branching speed | HB | CC | 5B105 | |
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.Control memory interleave | HB | CC | 5B105 | |
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Advanced controlling of micro-instructions using micro-programmes | HB | CC | 5B105 | |
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Others | HB | CC | 5B105 | |
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....Parallel processing | HB | CC | 5B105 | |
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..Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) [2018.01] | HB | CC | 5B033 | |
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...Decoding instructions | HB | CC | 5B033 | |
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Decoding of instructions in general | HB | CC | 5B033 | |
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Decoder configurations or layouts, e.g. pre-decoder | HB | CC | 5B033 | |
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selective switching of multiple decoders, e.g. multiple decoders to respond to multiple types of instruction sets | HB | CC | 5B033 | |
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Undefined or extended instructions, e.g. processing instructions not included in the instruction set by equivalent routine | HB | CC | 5B033 | |
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Processing instruction code errors | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Timing control e.g. changing instruction execution time, clock control | HB | CC | 5B033 | |
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Timing control in general | HB | CC | 5B033 | |
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selective switching of basic clock frequencies | HB | CC | 5B033 | |
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setting delay; or wait time | HB | CC | 5B033 | |
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Waiting for synchronization signal, e.g. waiting for response signals to synchronize with peripheral devices | HB | CC | 5B033 | |
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Timers | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Processing special instructions (variable length instruction or skip instruction G06f9/32) | HB | CC | 5B033 | |
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Processing special instructions in general; new instruction; instruction with predicate | HB | CC | 5B033 | |
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Execute instructions, e.g. for executing by assuming data fetched as an instruction operand of an instruction | HB | CC | 5B033 | |
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Database operation instructions | HB | CC | 5B033 | |
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Edit instructions on decimal data; packing conversion on decimal data; unpacking conversion on decimal data | HB | CC | 5B033 | |
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Combined instructions, e.g. VLIW | HB | CC | 5B033 | |
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Characterized being RIsC or PRIsM instructions | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...instructions specific to microcomputer | HB | CC | 5B033 | |
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...ALU peripheral configurations, improvement of CPU's internal bus or interconnection of register files and ALU, etc. | HB | CC | 5B033 | |
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...Generation or control of conditional code, e.g. zero flag | HB | CC | 5B033 | |
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...Measured for malfunctions | HB | CC | 5B033 | |
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Re-execution | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Device to run sub program | HB | CC | 5B033 | |
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....subroutine linkage | HB | CC | 5B033 | |
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subroutine in general | HB | CC | 5B033 | |
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Linkage Process, e.g. upload subroutine to main memory while running subroutine command | HB | CC | 5B033 | |
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Parameter delivery; Refer to parameter | HB | CC | 5B033 | |
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Address extension; address switching on an Identical space, e.g. for subroutine call between different segments and banks | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Malfunction countermeasure for device running subprogram | HB | CC | 5B033 | |
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....Others | HB | CC | 5B033 | |
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...Others | HB | CC | 5B033 | |
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...Controlling the executing of arithmetic operations [2018.01] | HB | CC | 5B033 | |
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Arithmetic operation in general | HB | CC | 5B033 | |
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Comparison in arithmetic operation | HB | CC | 5B033 | |
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Arithmetic operation of bytes or words; Zero extension; sign extension | HB | CC | 5B033 | |
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Constant processing in arithmetic operation; Generating fixed data in arithmetic operation | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Controlling the executing of logical operations [2018.01] | HB | CC | 5B033 | |
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Logic operation in general | HB | CC | 5B033 | |
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Comparison in logic operation | HB | CC | 5B033 | |
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Logic Operation on bytes or words | HB | CC | 5B033 | |
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Constant processing in logic operation; Generating fixed data in logic operation | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Controlling single bit operations (G06F9/305 takes precedence) [2018.01] | HB | CC | 5B033 | |
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Bit Operation in general | HB | CC | 5B033 | |
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Bit judgement; single bit operation command, e.g. population command, command to set or reset single bit | HB | CC | 5B033 | |
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Comparison of bit unit | HB | CC | 5B033 | |
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Operation process on bit | HB | CC | 5B033 | |
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Constant process on bit operation; Generation of fixed data on bit operation | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Controlling loading, storing or clearing operations [2018.01] | HB | CC | 5B033 | |
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Load, e.g. loading from memory to register | HB | CC | 5B033 | |
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store; Clear | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Controlling moving, shifting or rotation operations [2018.01] | HB | CC | 5B033 | |
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Move | HB | CC | 5B033 | |
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shift; Rotate; Alignment; shuffle; Merge; Mask | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...with operation extension or modification [2018.01] | HB | CC | 5B033 | |
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Instruction modification or change in general | HB | CC | 5B033 | |
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Modification, e.g. prefix | HB | CC | 5B033 | |
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Change; Total replacement | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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...Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence) [2018.01] | HB | CC | 5B033 | |
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....Processing instructions, e.g. addressing or fetching | HB | CC | 5B033 | |
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Addressing in general, e.g. increment program counter in sequence | HB | CC | 5B033 | |
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Memory access; memory fetching, e.g. serially fetching instructions from memory | HB | CC | 5B033 | |
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.Multiple memory modules configurations; memory space expansion, e.g. switching between banks or providing instruction memory and data memory separately | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Processing branching instructions, e.g. addressing or branching determination process | HB | CC | 5B033 | |
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Branch addressing in general | HB | CC | 5B033 | |
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Branch address computation; branch address creation | HB | CC | 5B033 | |
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.Creating indirect branching addresses | HB | CC | 5B033 | |
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.Creating multiple branching addresses; branching address modifications by conditions, e.g. generating multiple branch destination addresses or substitution of lower order bit group of branch destination address | HB | CC | 5B033 | |
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selective processing of next instruction or next address (G06f9/32, 320D, f take precedence), e.g. by selecting either Taken side address or Not Taken side address | HB | CC | 5B033 | |
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Conditions determination process; branching determination process; e.g. method directly related for a decision whether to branch or not to branch | HB | CC | 5B033 | |
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Jump between pages; jump amongst identical address space memories | HB | CC | 5B033 | |
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Memory access; memory fetch, e.g. a method of fetching a branch destination instruction from memory | HB | CC | 5B033 | |
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.Multiple memory modules configurations; memory space expansion, e.g. branch between memory banks | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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.....Loop processing | HB | CC | 5B033 | |
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Loop processing in general | HB | CC | 5B033 | |
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Repetitive processing of single instruction, e.g. suppressing increment of program counter | HB | CC | 5B033 | |
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Instruction buffers for loop | HB | CC | 5B033 | |
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Nest loop processing | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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.....instruction to skip instructions | HB | CC | 5B033 | |
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Pile up instructions, e.g. for executing only the first specific instruction and do not execute the following specific instruction without using a branch instruction | HB | CC | 5B033 | |
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skip instruction | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Variable length instructions; undefined length instructions; variable length operand formers | HB | CC | 5B033 | |
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Variable length instructions | HB | CC | 5B033 | |
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Variable length operand specifier, e.g. by the operand specifier field of the instruction word is in variable length | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....sequence controller | HB | CC | 5B033 | |
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sequence Controller in general | HB | CC | 5B033 | |
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Execution sequence control; branching for determining conditions | HB | CC | 5B033 | |
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Calculation processing | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Countermeasures for malfunctions while fetching instructions from memory | HB | CC | 5B033 | |
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....Designation jump address or return address for subprogram | HB | CC | 5B033 | |
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.....Jump addressing | HB | CC | 5B033 | |
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Jump addressing in general | HB | CC | 5B033 | |
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Generation and choice of multiple jump address | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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.....Return addressing | HB | CC | 5B033 | |
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Return addressing in general | HB | CC | 5B033 | |
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Generation and choice of multiple return address | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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......subroutine stack | HB | CC | 5B033 | |
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subroutine stack in general | HB | CC | 5B033 | |
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Hierarchical structure; Virtual stack | HB | CC | 5B033 | |
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stack error on subroutine | HB | CC | 5B033 | |
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Evacuate register block; switch between multiple registers, e.g. register window, register bank switch | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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.....Enable to be called from other routine by making a portion of main routine to be subroutine | HB | CC | 5B033 | |
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.....Run loop operation of subroutine | HB | CC | 5B033 | |
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.....Malfunction countermeasure on designation jump address or return address for subprogram | HB | CC | 5B033 | |
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.....Others | HB | CC | 5B033 | |
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....Others | HB | CC | 5B033 | |
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...Addressing or accessing the instruction operand or the result [2018.01] | HB | CC | 5B033 | |
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....Variable length operands | HB | CC | 5B033 | |
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Variable length operands in general | HB | CC | 5B033 | |
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Boundary control; alignment, e.g. for shifting or merging data to access operands that span two words of memory | HB | CC | 5B033 | |
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Bites processing; words processing, e.g. a 4-byte word is read out from the memory and one byte thereof is obtained | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Accessing registers | HB | CC | 5B033 | |
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....stacking (subroutine stacking G06f9/32, 384) | HB | CC | 5B033 | |
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stacking in general | HB | CC | 5B033 | |
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.Hierarchical structure; Virtual stack | HB | CC | 5B033 | |
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stacking errors, e.g. overflow or underflow | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Memory access | HB | CC | 5B033 | |
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Memory accesses in general | HB | CC | 5B033 | |
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.Multiple memory module configuration, e.g. bank interleave or bank switching (expansion of address space by index addressing G06f9/355, 330) | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Countermeasure for malfunction while operand fetching or operand storing | HB | CC | 5B033 | |
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....Others | HB | CC | 5B033 | |
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....of multiple operands or results [2018.01] | HB | CC | 5B033 | |
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In multiple operands or multiple results in general | HB | CC | 5B033 | |
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Using strides or intervals | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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....Indirect addressing [2018.01] | HB | CC | 5B033 | |
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....Indexed addressing [2018.01] | HB | CC | 5B033 | |
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.....Address modification in general | HB | CC | 5B033 | |
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......Address modification, e.g. index, base, page, relative, addition or location | HB | CC | 5B033 | |
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.......Address extension, e.g. address bit extension or memory space extension switch (Memory Module G06f12/06) | HB | CC | 5B033 | |
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Address extension in general | HB | CC | 5B033 | |
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Address bit extension, e.g. segment register | HB | CC | 5B033 | |
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Memory selection on identical address space, e.g. perform bank switch by assign identical address space to each bank | HB | CC | 5B033 | |
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Others | HB | CC | 5B033 | |
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.....Malfunction countermeasure relating address modification | HB | CC | 5B033 | |
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.....Others | HB | CC | 5B033 | |
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...Concurrent instruction execution, e.g. pipeline or look ahead [2018.01] | HB | CC | 5B013 | |
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....Preceding control, e.g. instructions prefetch, pipeline loading sequence control (vector processing G06f17/16) | HB | CC | 5B013 | |
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Instructions prefetch; operands prefetch; buffers | HB | CC | 5B013 | |
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.Calculating addresses | HB | CC | 5B013 | |
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Timing control; stage progress transition control | HB | CC | 5B013 | |
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Controlling the change of loading sequence to the pipelines, e.g. a subsequent instruction is loaded before preceding instructions, out of order or reorder buffer | HB | CC | 5B013 | |
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Vector instructions execution by pipeline method or parallel processing method (vector processing G06f17/16 take precedence) | HB | CC | 5B013 | |
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With variable length of instructions or operands, e.g. address calculation, fetching or cutting out due to being variable length | HB | CC | 5B013 | |
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Used in a pipeline mode in which computers are stacked in tandem | HB | CC | 5B013 | |
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Preceding control in general, e.g. arrange control memory at each pipeline stages | HB | CC | 5B013 | |
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.Other references; miscellaneous | HB | CC | 5B013 | |
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Others, e.g. with the use of preceding control instruction technology in applied fields | HB | CC | 5B013 | |
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....Branching control, e.g. branching destination prefetch, branching prediction, loop process | HB | CC | 5B013 | |
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Forecasting of branching | HB | CC | 5B013 | |
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.Branching history, e.g. a table reflecting past execution results, branching history table or branching target table | HB | CC | 5B013 | |
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.by fixedly setting predicted branching direction, e.g. having branching prediction flag in instruction, by externally fixedly set predicted branching direction | HB | CC | 5B013 | |
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.Early determination, e.g. condition codes, counting branch | HB | CC | 5B013 | |
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Loop process, e.g. branch prediction decision method with loop | HB | CC | 5B013 | |
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Prefetching branching destination instruction, e.g. branching destination instruction buffer, branching destination address computation or early detection of branching destination instruction | HB | CC | 5B013 | |
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.Restricting prefetching | HB | CC | 5B013 | |
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Conditional branching | HB | CC | 5B013 | |
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.Prospective executions, cancellation process | HB | CC | 5B013 | |
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Invalidation of already prefetched instruction and rereading instruction, e.g. EXECUTE instructions, serialization instruction or load PsW instruction | HB | CC | 5B013 | |
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Branching control in general | HB | CC | 5B013 | |
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.Other references; miscellaneous | HB | CC | 5B013 | |
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Others | HB | CC | 5B013 | |
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....storing control; fetch-store conflict, e.g. OsC, IsC or PsC | HB | CC | 5B013 | |
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fetch-store conflict, e.g. priority control, waiting or invalidation | HB | CC | 5B013 | |
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.Contents matching control, e.g. replacing prefetched contents, delivering data by bypass or forwarding, or register renaming | HB | CC | 5B013 | |
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storing control in general, e.g. R/W parallel control, left behind control | HB | CC | 5B013 | |
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.Other references; miscellaneous | HB | CC | 5B013 | |
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Others, e.g. with the use of branching control in applied fields | HB | CC | 5B013 | |
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....Parallel processing, e.g. multiple processing mechanisms or additional processing mechanisms (multi-processor G06f15/16) | HB | CC | 5B013 | |
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Multiple processing mechanisms or ALUs of same type | HB | CC | 5B013 | |
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Multiple processing mechanisms or ALUs by different type, e.g. multiple slots for realizing VLIW | HB | CC | 5B013 | |
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.Additional processing mechanisms, co-processor, e.g. for calculating floating decimal point, accelerator | HB | CC | 5B013 | |
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Parallel processing in general | HB | CC | 5B013 | |
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.Other references; miscellaneous | HB | CC | 5B013 | |
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Others, e.g. with the use of parallel processing in applied fields | HB | CC | 5B013 | |
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....Measures for malfunctions | HB | CC | 5B013 | |
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Processing for terminating interruptions; retry | HB | CC | 5B013 | |
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.Exception processing, e.g. address exception, protection or control at the time of interruption process | HB | CC | 5B013 | |
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Debugging; monitoring; tracing; testing, e.g. debugging by address matching | HB | CC | 5B013 | |
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Measures for malfunctions in general | HB | CC | 5B013 | |
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.Other references; miscellaneous | HB | CC | 5B013 | |
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Others, e.g. with the use of malfunction countermeasures related to simultaneous execution of instructions in applied fields | HB | CC | 5B013 | |
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....Others | HB | CC | 5B013 | |
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..Arrangements for executing specific programs [2018.01] | HB | CC | 5B376 | |
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...Bootstrapping (security arrangements therefor G06F21/57) [2018.01] | HB | CC | 5B376 | |
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...Program loading or initiating (bootstrapping G06F9/4401;security arrangements for program loading or initiating G06F21/57) [2018.01] | HB | CC | 5B376 | |
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....Dynamic loading; Link editing at or after load time | HB | CC | 5B376 | |
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....Program selecting | HB | CC | 5B376 | |
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....Memory management for program execution | HB | CC | 5B376 | |
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...Execution paradigms, e.g. implementations of programming paradigms [2018.01] | HB | CC | 5B107 | |
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....Procedural; Executing subprograms | HB | CC | 5B107 | |
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....Object-oriented | HB | CC | 5B107 | |
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...Execution arrangements for user interfaces [2018.01] | HB | CC | 5B376 | |
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...Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines [2006.01] | HB | CC | 5B107 | |
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....Interpreters; Runtime code interpretation or conversion | HB | CC | 5B081 | |
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....Hypervisor; Virtual machine monitor | HB | CC | 5B098 | |
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..Multiprogramming arrangements [2006.01] | HB | CC | 5B098 | |
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...Multi threading processor | HB | CC | 5B098 | |
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...Dispersed processing (Processing distribution being G06F9/46,465 precedence) | HB | CC | 5B098 | |
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Distributed object | HB | CC | 5B098 | |
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Movement agent | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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...Transaction processing | HB | CC | 5B098 | |
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...Program initiating; Program switching, e.g. by interrupt [2006.01] | HB | CC | 5B098 | |
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....Interrupt control (for bus interrupt, G06f13/24 takes precedence) | HB | CC | 5B098 | |
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Generating interruption | HB | CC | 5B098 | |
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Detecting status change | HB | CC | 5B098 | |
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By instruction, e.g. exception treating | HB | CC | 5B098 | |
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Key | HB | CC | 5B098 | |
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Debugging interruption | HB | CC | 5B098 | |
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Bank switching | HB | CC | 5B098 | |
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Extended interruption, e.g. addition to interrupt processing | HB | CC | 5B098 | |
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Timing | HB | CC | 5B098 | |
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Canceling interruption | HB | CC | 5B098 | |
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Interrupt processing during dynamic execution | HB | CC | 5B098 | |
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Measuring noise | HB | CC | 5B098 | |
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Interrupt function check | HB | CC | 5B098 | |
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Malfunction countermeasure during monitoring of interrupt signal | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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.....Receipt and detection of interrupt request | HB | CC | 5B098 | |
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Interruption receipt circuit | HB | CC | 5B098 | |
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Multiple interrupt receipt | HB | CC | 5B098 | |
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Receipt according to group | HB | CC | 5B098 | |
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Restricting interruption and mask | HB | CC | 5B098 | |
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Handling of holding interruption | HB | CC | 5B098 | |
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Detecting of interruption factor | HB | CC | 5B098 | |
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Cyclic scan | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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.....specifying interruption address, e.g. Interruption vector | HB | CC | 5B098 | |
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.....Interruption while executing command | HB | CC | 5B098 | |
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Return to checkpoint | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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.....Timer interrupt | HB | CC | 5B098 | |
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Timer correction | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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.....Priority interruption | HB | CC | 5B098 | |
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Controlling switching of program level | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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......Priority circuit | HB | CC | 5B098 | |
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......Changing to priority | HB | CC | 5B098 | |
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Even allocation, e.g. round robin | HB | CC | 5B098 | |
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Emergency interrupt | HB | CC | 5B098 | |
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Allocating according to processing request | HB | CC | 5B098 | |
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Changing according to time, e.g. allocating according to waiting time | HB | CC | 5B098 | |
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switching priority circuit | HB | CC | 5B098 | |
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Priority circuit using memory | HB | CC | 5B098 | |
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setting priority according to program, e.g. priority register | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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......first-in priority | HB | CC | 5B098 | |
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....scheduling and task dispatch (Interrupt control being G06f9/48,100 takes precedence) | HB | CC | 5B098 | |
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Job scheduling, e.g. starting specification by using calendar | HB | CC | 5B098 | |
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One that priority level being changed (Interrupt control being G06f9/48,220 takes precedence) | HB | CC | 5B098 | |
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Handling queue, e.g. Dequeuing, enqueuing, and switching queue of multiple number/operation | HB | CC | 5B098 | |
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Time sharing Tss | HB | CC | 5B098 | |
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.One that timesharing unit to be variable | HB | CC | 5B098 | |
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One based on deadline | HB | CC | 5B098 | |
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One based on load condition (Processing distribution being G06f9/50,150 takes precedence) | HB | CC | 5B098 | |
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One having added attribute to tasks, e.g. execution condition, authority, and initial value | HB | CC | 5B098 | |
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Monitoring tasks, processes etc. | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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....Information saving, e.g. task context save | HB | CC | 5B098 | |
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Partial saving of information | HB | CC | 5B098 | |
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One using stack or register | HB | CC | 5B098 | |
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.switching registers, e.g. having multiple sets of registers | HB | CC | 5B098 | |
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.Combined use of register switching and saving | HB | CC | 5B098 | |
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switching program counters | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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....Interdependent control of tasks; Cooperation between tasks (Interprogram communication being G06f9/54 takes precedence) | HB | CC | 5B098 | |
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...Allocation of resources, e.g. of the central processing unit [CPU] [2006.01] | HB | CC | 5B098 | |
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....Management of hardware resources | HB | CC | 5B098 | |
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Resource allocation to tasks | HB | CC | 5B098 | |
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.Based on priority level | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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....Process allocation for processing entities | HB | CC | 5B098 | |
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Based on characteristics of processing entities, e.g. function or ability of hardware resources | HB | CC | 5B098 | |
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.Combining multiple number services | HB | CC | 5B098 | |
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Based on characteristic of contents to be processed | HB | CC | 5B098 | |
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Based on load condition of processing entities | HB | CC | 5B098 | |
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Dividing process into tasks | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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...Program synchronisation; Mutual exclusion, e.g. by means of semaphores [2006.01] | HB | CC | 5B098 | |
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....Mutual exclusion, e.g. locks or semaphores | HB | CC | 5B098 | |
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Detecting or preventing deadlock | HB | CC | 5B098 | |
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Exclusive control algorithm | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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....synchronous control; Maintain consistency | HB | CC | 5B098 | |
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Matching with the execution of other tasks, e.g. barrier-sync | HB | CC | 5B098 | |
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Maintain consistency of process condition, etc. | HB | CC | 5B098 | |
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Maintain data consistency without dependency on system configuration | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |
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...Interprogram communication [2006.01] | HB | CC | 5B098 | |
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Through shared data area | HB | CC | 5B098 | |
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Using message queue | HB | CC | 5B098 | |
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Event | HB | CC | 5B098 | |
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RPC | HB | CC | 5B098 | |
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Message structure | HB | CC | 5B098 | |
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Message conversion, e.g. wrappers or brokers | HB | CC | 5B098 | |
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Others | HB | CC | 5B098 | |