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5F048 METAL-OXIDE SEMICONDUCTOR INTEGRATED CIRCUITS (MOSIC) AND BIPOLAR METAL-OXIDE SEMICONDUCTOR INTEGRATED CIRCUITS (BI-MOSIC)
H10D84/40 -84/40@Z;84/80-84/80,102@Z;84/82-84/85@Z;84/90;84/90,102;87/00
H01L27/06,102-27/06,331;27/07,102;27/085-27/092@Z;27/118;27/118,102 AA AA00
PURPOSE 		AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10
. Large-scale integration . Protection against an overvoltage on metal-oxide semiconductor (MOS) gates . Prevention of latch-up and of parasitic bipolar . Element separation . Increase of breakdown voltage . Improvement of radiation resistance e.g. alpha-ray resistance . Improvement of reliability . Improvement of mutual conductance of MOS . Reduction of manufacturing processes . Improvement of bipolar-transistor characteristics
AB AB00
USE 		AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB10
. Memory . Master slices or gate arrays . Logic circuits . . Inverter circuits . . Buffer circuits . Input circuits . Output circuits . Reference voltage generating circuits . Others
AC AC00
INTEGRATED CIRCUIT ELEMENT 		AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10
. Metal oxide semiconductor (MOS) elements with metal oxide semiconductor (MOS) elements . . Enhancement and depletion metal-oxide semiconductors (E-D MOS) or enhancement and enhancement metal-oxide semiconductors (E-E MOS) . . Complementary metal-oxide semiconductors (CMOS) . . . Thin-film transistor complementary metal-oxide semiconductors (TFT CMOS) . . Bipolar complementary metal-oxide semiconductors (Bipolar-CMOS) . . including power metal oxide semiconductors (MOS) . including bipolar transistors (BiCMOS is classified in AC05.) . . Bi-MOS composite elements . including static induction transistor (SIT) junction field effect transistor (JEFT) metal semiconductor field effect transistor (MESFET) . including inductance (L) capacitance (C) or resistance elements (R) or diodes
BA BA00
SUBSTRATE 		BA01 BA02 BA03 BA04 BA05 BA06 BA07 BA09 BA10
. Monolayer substrates . Multi-layer substrates e.g. two layers . . Three or more layers . . . with first and second epitaxial layers being the same type . . . with first and second epitaxial layers being different types . . with substrate and directly above layers being the same type . . with substrate and directly above layer having mutually different types . having insulating layers in substrates . characterised by crystal faces or crystal axes
BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA19 BA20
. adding carrier-recombination centres into substrates . Buried layers . . Double buried layers . Element formation regions or active regions formed of materials other than silicon (Si) . . Group III-V compound semiconductors . Insulating substrates . . Silicon on sapphire (SOS) . Electrodes for multiple metal-oxide semiconductor (MOS) elements being on different planes . part of metal-oxide semiconductor (MOS) being formed on insulating film
BB BB00
GATE 		BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10
. Shapes . . Divided gates or multiple gates . . A plurality of MOS with different gate lengths . Materials . . Polycrystalline silicon (Si) . . . N-type doped polycrystalline silicon (Si) . . . P-type doped polycrystalline silicon (Si) . . Silicides . . Metals alloys or metal compounds excluding silicides . . A plurality of metal-oxide semiconductors (MOS) using different materials for gate electrodes
BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20
. . characterised by materials for gate-insulating films . Multi-layer or two-layer gates . . Three or more metal layers . Threshold control . . A plurality of metal-oxide semiconductors (MOS) with different threshold voltages . . . with insulating-films having different thicknesses . . . with different insulating materials . . . with different amounts of implantation or different materials to be implanted . Buried gates . Specially structured gates e.g. V-shaped gates
BC BC00
SOURCE AND DRAIN 		BC01 BC02 BC03 BC05 BC06 BC07
. Shapes . . Divided drains and sources . Asymmetrical structures . Formation of additional regions . . Lightly doped drains (LDD) . . Double diffusion
BC11 BC12 BC15 BC16 BC18 BC19 BC20
. Insulating layers beneath sources and drains . taking out reverse electrodes . Materials . . Polycrystalline silicon (Si) e.g. silicon on insulator (SOI) . A plurality of metal-oxide semiconductors (MOS) with mutually different source and drain regions . . different in depth . . different in concentration
BD BD00
CHANNEL 		BD01 BD02 BD04 BD05 BD06 BD07 BD09 BD10
. Shapes . . characterised by length or width of channels . having additional ions implanted in channels . Buried channels . characterised by electric current direction . . Vertical channels see CB07 . forming channel regions separately by epitaxial growth . characterised by channel lengths or widths between a plurality of metal-oxide semiconductors (MOS)
BE BE00
WELL 		BE01 BE02 BE03 BE04 BE05 BE06 BE07 BE08 BE09 BE10
. characterised by distribution of impurity concentrations . Double wells . Dual wells [P and N] . Multiple wells of the same type . A plurality of wells with different depths . A plurality of wells with different concentrations . Wells deeper than surface epitaxial layers . Complementary metal-oxide semiconductors (CMOS) without wells . impressing voltage onto wells . Others
BF BF00
WIRING, ELECTRODE AND CONTACT 		BF01 BF02 BF03 BF04 BF05 BF06 BF07 BF08
. Materials . . Aluminium (Al) . . Polycrystalline silicon (Si) . . . N-type doped polycrystalline silicon (Si) . . . P-type doped polycrystalline silicon (Si) . . Silicides . . Metals alloys or metal compounds excluding silicides . . Superconducting materials
BF11 BF12 BF15 BF16 BF17 BF18 BF19
. Multi-layer wiring with two layers . . Three or more layers . Contact between gate electrodes and wiring . Contact between sources and drains and wiring . Regions having reduced contact resistance with sources or drains. . Substrate or well contact regions . Contacts for connection of gates with gates
BG BG00
INSULATOR ISOLATION 		BG01 BG02 BG03 BG05 BG06 BG07
. Materials . . Phosphosilicate glass (PSG) . . Silicon nitride (Si3N4) . separating side surfaces and bottom surfaces of element regions by means of insulator . . only a portion of a plurality of metal-oxide semiconductors (MOS) or complementary metal-oxide semiconductors (CMOS) . . all of the plurality metal-oxide semiconductors (MOS) or complementary metal-oxide semiconductors (CMOS)
BG11 BG12 BG13 BG14 BG15 BG16
. separating only side surfaces of element regions by insulation . . Separation by selective oxidation e.g. local oxidation of silicon (LOCOS) . . Trench or groove separation . . . burying insulation other than SiO2 in grooves . . . implanting ions into substrate layers beneath grooves . . V-grooves
BH BH00
PN JUNCTION ISOLATION 		BH01 BH02 BH03 BH04 BH05 BH06 BH07 BH08 BH09
. PN junction isolation in both side surfaces and bottom surfaces of element regions . using PN junction isolation only in side surfaces of element regions . using PN junction isolation only in bottom surfaces of element regions . Application of potential to isolation regions . Guard rings or guard bands . . with a plurality of guard rings formed . Channel stoppers . . Double channel stoppers . Cut layers
CA CA00
STRUCTURE OF BIPOLAR TRANSISTOR 		CA01 CA02 CA03 CA04 CA05 CA06 CA07 CA08 CA09 CA10
. formed within wells . formed on one-layer substrates . formed on epitaxial layers on substrates . forming in insulation separation region . forming in PN junction isolation regions . forming on planes different from metal-oxide semiconductors (MOS) . Buried layers beneath bipolar transistors . Buried bases . Double-diffusion bases . Divided bases
CA12 CA13 CA14 CA15 CA16 CA17
. Well collectors . Silicide contacts e.g. emitters bases or collectors . Polycrystalline silicon (Si) wiring e.g. from emitters bases or collectors . Emitter side walls . A plurality of bipolar transistors with different breakdown voltages . Multi-layer wiring
CB CB00
THREE-DIMENSIONAL METAL-OXIDE SEMICONDUCTOR INTEGRATED CIRCUITS (MOSIC), INCLUDING BIMOS 		CB01 CB02 CB03 CB04 CB06 CB07 CB08 CB10
. Stacked metal-oxide semiconductor integrated circuits (MOSIC) e.g. in two layers . . Three or more layers . . Contacts between layers . . Wiring between layers . Vertical metal-oxide semiconductor integrated circuits (MOSIC) and double gate MOS . . Vertical channels see BD07 . . Double gates mutually facing in the vertical direction . Forming other metal-oxide semiconductors (MOS) corresponding to gate electrodes
CC CC00
COMPONENT OF PROTECTIVE CIRCUITS 		CC01 CC02 CC03 CC04 CC05 CC06 CC07 CC08 CC09 CC10
. Resistor . . Arrangements and shapes . . Materials . . . Polycrystalline silicon (Si) . Capacitors . Diodes . . Diodes between protected elements . Metal-oxide semiconductors (MOS) . . Two or more metal-oxide semiconductors (MOS) . Bipolar thyristor
CC11 CC12 CC13 CC14 CC15 CC16 CC17 CC18 CC19 CC20
. Arrangement (Arrangements and shapes only for resistors are classified in CC02.) . provided with constant voltage or constant current circuits . impressing voltage onto wells or substrates . Circuits for detecting and releasing latch-up . providing on the input side . providing on the output side . Object to be protected . . Metal-oxide semiconductor integrated circuits (MOSIC) . . Complementary metal-oxide semiconductor integrated circuits (CMOSIC) . . Bi-MOS (Bipolar metal-oxide semiconductor) or Bi-CMOS (Bipolar complementary metal oxide semiconductor) integrated circuits
DA DA00
MANUFACTURING METHOD 		DA01 DA02 DA03 DA04 DA05 DA06 DA07 DA08 DA09 DA10
. simultaneously forming together with source and drain of one metal-oxide semiconductor (MOS) . . Two metal-oxide semiconductor (MOS) guard rings . . Two metal-oxide semiconductor (MOS) channel stoppers . . One or two metal-oxide semiconductor (MOS) gates e.g. polycrystalline silicon (Si) . . Two metal-oxide semiconductor (MOS) wells . . Bipolar transistor collectors . . Bipolar transistor bases . . Bipolar transistor emitters . Simultaneous formation of two or more elements excluding sources and drains . . Wells
DA11 DA12 DA13 DA14 DA15 DA17 DA18 DA19 DA20
. . Guard rings . . Channel stoppers . . Bases . . Collectors . . Emitters . Layers to protect gates during ion implantation excluding the outermost resist layers . . Silicon dioxide (SiO2) . . Silicon nitride (Si3N4) . . High melting point metals
DA21 DA22 DA23 DA24 DA25 DA26 DA27 DA28 DA29 DA30
. . High melting point metal silicides . . Aluminium oxide (Al203) . Gate side walls . . Materials . . . Silicon dioxide (SiO2) . . . High melting point metal silicides . . . Silicon nitride (Si3N4) . . . polycrystalline silicon (Si) . . . Phosphosilicate glass (PSG) . . Double side walls
DB DB00
FORMING DIFFUSION LAYERS OTHER THAN BY ION IMPLANTATION 		DB01 DB02 DB03 DB04 DB05 DB06 DB07 DB08 DB09 DB10
. Diffusion sources . . Phosphosilicate glass (PSG) . . Borosilicate glass (BSG) . . Polycrystalline silicon (Si) doped with impurities . Regions formed . . Source and drain . . Channel stoppers . . Bases . . Emitters . . Collectors
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